Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 High-End FPGAs
      About Stratix Series
   Stratix IV (E and GX)
   Stratix III (L and E)
   Stratix II (and GX)
   Stratix (and GX)
  
 Midrange FPGAs
   Arria (GX)
  
 Low-Cost FPGAs
   Cyclone III
       Overview
               Architecture
               Power
          End Markets & Applications
          Design Resources
          Literature
          Getting Started
   Cyclone II
   Cyclone
  
 CPLDs
   MAX II (and G, Z)
   MAX 3000A
  
 ASICs
      About HardCopy Series
   HardCopy IV (E and GX)
   HardCopy III
   HardCopy II
   HardCopy Stratix
  
 Device-Specific Offerings
   RoHS Compliant
      Extended Temperature
      Industrial Temperature
      Military Temperature
      Automotive Temperature
  
 Configuration Devices
   Enhanced Configuration
   Serial Configuration
  
 Mature Products
      Product Listing
  

Differences Between Cyclone II and Cyclone III FPGAs

Table 1. Cyclone® II and Cyclone III Feature Comparison
Feature Device
Cyclone II Cyclone III
Cost-Optimized Architecture
  • 30% lower cost than Cyclone FPGAs (on a cost-per-logic-element basis)
  • 20% lower cost than
    Cyclone II FPGAs (on a cost-per-logic-element basis)
Process Technology
  • 90-nm
  • Low-K dielectric process
  • Built on 300-mm wafers
  • TSMC's 65-nm low-power (LP) process 
  • Low-K dielectric process
  • Built on 300-mm wafers
Core Voltage
  • 1.2 V
  • 1.2 V
I/O Voltage
  • 1.5 V, 1.8 V, 2.5 V, 3.3 V
  • 1.5 V, 1.8 V, 2.5 V, 3.3 V
Logic Density
  • 4,608 to 68,416 logic elements (LEs)
  • 5,136 to 119,088 LEs
I/O Pin Count
  • 85 to 622
  • 82 to 535
Embedded Memory
  • M4K RAM blocks
  • Up to 1.1 Mbits of on-chip memory
  • 216-MHz performance
  • M9K RAM blocks
  • Up to 4 Mbits of on-chip memory
  • 260-MHz performance
External Memory Interface Support
  • SDR, DDR, DDR2, QDRII
  • 167-MHz DDR2
  • SDR, DDR, DDR2,
    QDR II
  • 200-MHz DDR2
Digital Signal Processing (DSP) Implementation
  • Up to 150 18 x 18 multipliers
  • Up to 288 18 x 18 multipliers
PLLs
  • 2 to 4 phase-locked loops (PLLs) per device with up to 12 PLL outputs
  • 2 to 4 PLLs per device with up to 20 PLL outputs
  • PLLs can be cascaded
  • PLLs dynamically configurable
Clock Networks
  • Up to 16 dedicated global clocks (GCLK) and 20 dual-purpose clocks per device
  • Up to 20 dedicated global clocks
I/O Standards Support
  • LVDS, mini-LVDS, LVPECL, RSDS, SSTL, HSTL, PCI, PCI-X, LVTTL, LVCMOS
  • LVCMOS, LVPECL, LVDS, mini-LVDS, RSDS, PPDS, SSTL, HSTL, PCI-X, LVTTL
  • All standards supported on all banks
  • Dedicated LVDS output buffers
  • LVDS TX 840 Mbps
  • LVDS RX 875 Mbps
Nios® II Embedded Processor Support
  • Yes
  • Yes
Packages
  • 144-pin TQFP
  • 208-pin PQFP
  • 240-pin PQFP
  • 256-pin FineLine BGA
  • 484-pin Ultra FineLine BGA
  • 484-pin FineLine BGA
  • 672-pin FineLine BGA
  • 896-pin FineLine BGA
  • 144-pin EQFP
  • 240-pin PQFP
  • 256-pin 1 mm pitch FBGA
  • 324-pin 1 mm pitch FBGA
  • 484-pin 1 mm pitch FBGA
  • 780-pin 1 mm pitch FBGA
  • 256-pin .8 mm pitch UBGA
  • 484-pin .8 mm pitch UBGA

 

Next Steps

Buy Now

Support

Documentation

  Please Give Us Feedback