Delivering the World's First Low-Cost 65-nm FPGAs
Altera's strategy for delivering the Cyclone® III family focuses on leveraging advanced technologies and methods to provide the most capable devices at the lowest cost, while minimizing risk and ensuring short time-to-market for customers. To that end, Altera has been steadily developing and testing its 65-nm technology since early 2003.
Learn about Altera’s investment in delivering the world’s first low-cost 65-nm FPGAs:
Challenges at the 65-nm Process Node
The 65-nm process presented specific product definition, design, and delivery challenges as semiconductor fabrication techniques were pushed to new limits. Undesirable deep submicron effects, including process variation and parametric failures that were manageable at 130- and 90-nm channel lengths, become pronounced engineering challenges with the 65-nm process.
At smaller geometries, variability in the manufacturing process has a much greater impact on device operation. These variations present significant challenges in submicron semiconductor manufacturing, and become even more severe as the space between transistors is reduced. Parasitic resistive and capacitive effects resulting from layout also represent significant hurdles to manufacturing at submicron levels, because they impact timing and signal integrity, and are increasingly difficult to model and analyze.
Static power can increase dramatically with the 65-nm semiconductor process if no power-reduction strategies are employed. Static power consumption rises at sub-micron process technologies largely because of increases in leakage current, including tunneling current across the thinner gate oxides that are used in the 65-nm process, as well as subthreshold leakage (channel- and drain-to-source current). Also, without any specific power optimization effort, dynamic power consumption can increase because of the higher density of switching transistors combined with the higher switching frequencies that are attainable.
Altera applied the latest techniques to minimize the negative impacts of variation and increased power consumption in 65-nm manufacturing in a strategy that includes advanced architecture enhancements, comprehensive test chip and device checkout programs, and reliance on the industry’s strongest foundry partnership.
Cyclone III Architecture and Process Features
Altera has taken significant steps to reduce static and dynamic power in Cyclone III devices, including different oxide thicknesses, multiple transistor threshold voltages, variable gate-length transistors, and use of low-K dielectrics.
Figure 1. TSMC 65-nm Process
With Cyclone III FPGAs, Altera employs multiple oxide thicknesses, using thicker gate oxides for noncritical speed transistors to lower the leakage current flowing through those transistors, which in turn, reduces static power consumption (refer to Figure 1). Using multiple threshold voltages provides the opportunity to use higher threshold voltages for noncritical speed transistors to again reduce leakage current.
The gate or channel length of a transistor affects its speed and subthreshold leakage. As the length of a transistor approaches the minimum gate length of the 65-nm process, the subthreshold leakage current increases significantly. Altera uses longer gate lengths to reduce leakage current in circuits where performance is not required, and short gate lengths where performance is critical. Altera also uses low-k dielectrics in Cyclone III FPGAs to insulate metal layers, which reduces capacitance and has a direct relationship with reducing dynamic power consumption.
Comprehensive and Rigorous From Start to Finish: From Test Chips to Device Checkout
Altera demonstrated with its 130-nm and 90-nm devices that test chips were a valuable tool for early evaluation and refinement of architecture and device features on new semiconductor processes. This strategy helped Altera achieve smooth ramps to volume production of these devices. Altera taped out its first 65-nm test chips in April 2003, the first of 11 test chips designed to carefully evaluate different circuits, modules, and design techniques.
Altera's test-chip program, the most comprehensive in the industry, allows evaluation of all the elements of the 65-nm process well in advance of product introduction. With each successive test chip, Altera implements additional features and architectural elements to truly characterize and prove its designs. By collecting and analyzing the test-chip data, Altera gains valuable insight into the impact of random and systematic variations, and is able to develop design strategies to reduce or eliminate them.
The process that begins with test chips ends with a device checkout. Altera performs a rigorous device checkout, encompassing the development and manufacturing stages, to ensure that all of its silicon products operate exactly as specified. The checkout is composed of many steps involving multiple Altera teams from IC design, layout, product engineering, reliability, and applications engineering. By applying these rigorous test and checkout procedures to every product, Altera ensures the highest levels of quality and reliability, as well as availability.
The Strongest Foundry Partnership in the Industry
Altera's foundry partner, TSMC, is the foundry market leader. TSMC has over 50 percent of the worldwide market share among dedicated foundries and an annual research and development investment 55 percent greater than its nearest competitor. These investments have resulted in industry-leading positions in lithography and design-for-manufacturability (DFM) that further ensure TSMC's success in delivering products at advanced process generations.
Altera and TSMC have a long-standing commitment to each other to pursue advanced process technologies. One of the most significant results of the Altera-TSMC partnership has been the steady reduction in defect densities achieved in Altera's products through the companies' joint efforts. Defects in the silicon process are inevitable, and defect densities are often quite high during the early part of a new process.
Over the last five process generations, Altera and TSMC have not only reduced defect densities effectively, but have accelerated this reduction. This coordinated effort to drive defect density reduction has taken many process generations to develop.
Accompanying Altera in partnering with TSMC to develop the 65-nm process are several other semiconductor industry leaders, including Broadcom, QUALCOMM, and Freescale. With these major semiconductor vendors driving its process technology, TSMC is in a unique position among dedicated foundries to deliver the highest reliability and quality in its 65-nm manufacturing.
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