Cyclone III FPGAs—Optimized for Low Power
Altera's Cyclone® III FPGAs are optimized for low power to help you manage thermal requirements, reduce or eliminate system cooling costs, and extend battery life for handheld applications. The Cyclone III device family is the first to offer an FPGA with up to 120K logic elements (LEs) that consumes less than 0.5 watts of static power.
Learn about Altera’s investment in delivering the low-power Cyclone III family:
Cyclone III FPGA Power Consumption
Figure 1 shows typical power consumption for Cyclone III family FPGAs at different operating frequencies. At a representative operating frequency such as 20 MHz, the largest Cyclone III device, the 120K LE EP3C120, consumes less than 600 mW of power. Even at operating frequencies as high as 100 MHz, the EP3C120 consumes less than two watts of power.
Figure 1. Typical Power Consumption of Cyclone III FPGAs
Static power can increase dramatically with the 65-nm semiconductor process if no power-reduction strategies are employed. Static power consumption rises at sub-micron process technologies largely because of increases in leakage current (including tunneling current across the thinner gate oxides that are used in the 65-nm process), as well as subthreshold leakage (channel- and drain-to-source current). Altera has taken significant steps to reduce static power in Cyclone III devices, described in Silicon and Architectural Optimizations.
Figure 2 shows the static power consumption of Cyclone III devices at 25°C and 85°C junction temperature. The smallest Cyclone III device consumes as little as 35 mW at 25°C, and the largest Cyclone III device consumes as little as 170 mW static power at 85°C.
Figure 2. Typical Static Power Consumption of Cyclone III FPGAs
Benefits of Low Power Consumption
Reducing the power consumption of programmable logic devices carries far-reaching benefits for lots of applications including:
- Portable or handheld battery-powered devices
- Space-constrained and other thermally challenging environments
- Price-sensitive applications where cooling systems are not cost effective
The Cyclone III family is an excellent example of Altera’s leadership in offering the lowest power FPGAs. Combining a comprehensive approach of architecture and silicon enhancements, the latest semiconductor process technology, and complete power management tools for customers, Altera’s efforts have resulted in up to a 50 percent reduction in power consumption compared to 90nm-based Cyclone II FPGAs, and the lowest power consumption of any comparable FPGAs.
Silicon and Architectural Optimizations
Cyclone III FPGAs are developed on Taiwan Semiconductor Manufacturing Company's (TSMC’s) 65-nm low-power (LP) process technology, which is also employed by other major semiconductor manufacturers for handset components. The smaller geometries made possible by this advanced process combined with architectural optimizations enable Cyclone III devices to deliver up to 30 percent lower total power consumption compared to 90nm-based Cyclone II devices by keeping dynamic and static power consumption to a minimum. The process and architectural enhancements that Altera employs with Cyclone III devices includes the use of low-k dielectrics, variable channel lengths and oxide thicknesses, and multiple transistor threshold voltages. For more information on these enhancements, see Delivering the World's First Low-Cost 65-nm FPGAs.
Accurate Power Estimation and Analysis
Altera supports power estimation and analysis from design concept through implementation, with the most accurate and complete power management design tools. Underscoring its commitment to accuracy in power analysis, Altera is the only programmable logic vendor that offers 85°C and worst-case silicon power estimates for its low-cost families throughout its tool suite. Altera offers the following power estimation and analysis resources:
When designing, you would use the PowerPlay early power estimator (EPE) during the design concept phase and the PowerPlay power analyzer during the design implementation phase. The PowerPlay EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization.
The PowerPlay power analyzer is a far more detailed power analysis tool that uses actual design placement and routing and logic configuration, and can use simulated waveforms to estimate dynamic power very accurately. The power analyzer, in aggregate, usually provides ± 10 percent accuracy when used with accurate design information. Quartus II PowerPlay power models closely correlate to actual silicon measurements. Altera uses over 5,000 different test configurations to measure the power of individual components within a Cyclone series device. Each configuration is focused on measuring a single circuit component of the FPGA in a specific configuration.
Quartus II Power Optimization
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area trade-offs have been automated within the register transfer level (RTL) through the place-and-route design flow. Altera has taken a leadership position in bringing power optimization into the design flow. Quartus II PowerPlay optimization tools automatically use the Cyclone III architecture capabilities to reduce power further, resulting in up to 25 percent lower dynamic power consumption compared to Cyclone II devices. Combined with the silicon and architecture enhancements in the Cyclone III family, these efforts have resulted in up to a 50 percent reduction in power consumption compared to 90nm-based Cyclone II FPGAs.
Quartus II software has many automatic power optimizations that are transparent to the designer but provided optimal utilization of FPGA architecture details to minimize power, including:
- Transforming major functional blocks
- Mapping user RAMs so they use less power
- Restructuring logic to reduce dynamic power
- Correctly selecting logic inputs to minimize capacitance on high-toggling nets
- Reducing area and wiring demand for core logic to minimize dynamic power in routing
- Modifying placement to reduce clocking power
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