Altera's Cyclone® III FPGAs are optimized for low power to help you manage thermal requirements, reduce or eliminate system cooling costs, and extend battery life for handheld applications. Cyclone III and Cyclone III LS devices are the first FPGAs with up to 200K logic elements (LEs) that consume less than 0.25 watts of static power.
- View the free Reduce Power Consumption and Thermal Dissipation Using New Low-Cost FPGAs webcast
Learn about Altera’s investment in delivering the low-power Cyclone III family:
- Cyclone III FPGA power consumption
- Benefits of low power consumption - It’s more than better battery life
- Silicon and architecture optimizations
- Accurate power estimation and analysis
Cyclone III FPGA Power Consumption
Static power can increase dramatically with the sub-micron semiconductor process if no power-reduction strategies are employed. Static power consumption rises at sub-micron process technologies largely because of increases in leakage current (including tunneling current across the thinner gate oxides), as well as subthreshold leakage (channel- and drain-to-source current). Altera has taken significant steps to reduce static power in Cyclone III devices, as described in Silicon and Architectural Optimizations.
Figure 1 shows the static power consumption of Cyclone III devices at 85°C junction temperature. The smallest Cyclone III device, the EP3C5 device, consumes as little as 50 mW at 85°C, and the largest Cyclone III FPGA, the EP3CLS200 device, consumes as little as 238 mW static power at 85°C.
Figure 1. Typical Static Power Consumption of Cyclone III FPGAs
Benefits of Low Power Consumption
Reducing the power consumption of programmable logic devices carries far-reaching benefits for many applications including:
- Portable or handheld battery-powered devices
- Space-constrained and other thermally challenging environments
- Price-sensitive applications where cooling systems are not cost effective
The Cyclone III FPGA family is an excellent example of Altera’s leadership in offering the lowest power FPGAs. Combining a comprehensive approach of architecture and silicon enhancements, the latest semiconductor process technology, and complete power management tools for customers, Altera’s efforts have reduced power consumption by up to half compared to 90-nm Cyclone II FPGAs, and have resulted in the lowest power consumption of any comparable FPGAs.
Silicon and Architectural Optimizations
Cyclone III FPGAs are developed on Taiwan Semiconductor Manufacturing Company's (TSMC’s) low-power (LP) process technology, which is also employed by other major semiconductor manufacturers for handset components. The smaller geometries made possible by this advanced process, combined with architectural optimizations, enable Cyclone III FPGAs to keep dynamic and static power consumption to a minimum. These silicon and architectural optimizations alone deliver up to 60 percent of the overall lower total power consumption savings compared to 90-nm Cyclone II FPGAs. The process and architectural enhancements that Altera employs with Cyclone III FPGAs includes the use of low-k dielectrics, variable channel lengths and oxide thicknesses, and multiple transistor threshold voltages. For more information on these enhancements, see Delivering the World's First Low-Cost 65-nm FPGAs.
Accurate Power Estimation and Analysis
Altera supports power estimation and analysis, from design concept through implementation, with the most accurate and complete power management design tools. Underscoring this commitment to accuracy in power analysis, Altera is also the only programmable logic vendor that offers 85°C and worst-case silicon power estimates for its low-cost FPGA families throughout its tool suite. Altera offers the following power estimation and analysis resources:
- Cyclone III Early Power Estimator
- Quartus® II PowerPlay Power Analysis and Optimization Technology
- Power Management Resource Center
When designing, you would use the PowerPlay early power estimator (EPE) during the design concept phase and the PowerPlay power analyzer during the design implementation phase. The PowerPlay EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization.
The PowerPlay power analyzer is a far more detailed power analysis tool that uses actual design placement and routing and logic configuration, and can use simulated waveforms to very accurately estimate dynamic power. The power analyzer, in aggregate, usually provides ± 10 percent accuracy when used with accurate design information. The Quartus II PowerPlay power models closely correlate to actual silicon measurements. Altera uses over 5,000 different test configurations to measure the power of individual components within a Cyclone series FPGA. Each configuration is focused on measuring a single circuit component of the FPGA in a specific configuration.
Quartus II Power Optimization
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area trade-offs have been automated within the register transfer level (RTL) through the place-and-route design flow. Altera has taken a leadership position in bringing power optimization into the design flow. Quartus II PowerPlay optimization tools automatically use the Cyclone III FPGA architecture capabilities to reduce power further, resulting in up to 25 percent lower dynamic power consumption compared to Cyclone II FPGAs. Combined with the silicon and architecture enhancements in the Cyclone III FPGA family, these efforts have resulted in up to a 50 percent reduction in power consumption compared to 90-nm Cyclone II FPGAs.
Quartus II development software has many automatic power optimizations that are transparent to the designer but provide optimal utilization of the FPGA architecture to minimize power, including:
- Transforming major functional blocks
- Mapping user RAMs so they use less power
- Restructuring logic to reduce dynamic power
- Correctly selecting logic inputs to minimize capacitance on high-toggling nets
- Reducing area and wiring demand for core logic to minimize dynamic power in routing
- Modifying placement to reduce clocking power
Related Links
- White paper: Achieving Low Power in 65-nm Cyclone III FPGAs (PDF)
- White paper: Altera's Strategy for Delivering the Benefits of the 65-nm Semiconductor Process (PDF)
- Quartus II Handbook Volume 2, Chapter 9. Power Optimization (PDF)
- Cyclone III Early Power Estimator
- Quartus II PowerPlay Power Analysis & Optimization Technology
- Power Management Resource Center
- Delivering the World's First Low-Cost 65-nm FPGAs
- Webcast: Reduce Power Consumption & Thermal Dissipation Using Low-Power, Low-Cost FPGAs
