FLEX 8000 Device Family
The FLEX 8000 family offers devices ranging from 2,500 to 16,000 gates with fast, predictable interconnect delays. The FLEX 8000 family combines the high speed, predictable timing, and ease-of-use of EPLDs with the high register count, low standby power, and in-circuit reconfigurability (ICR) of FPGAs.
The FLEX 8000 architecture consists of silicon-efficient, fine-grained logic elements grouped into high-performance, coarse-grained LABs. This dual granularity enables the FLEX 8000 family to offer both the fast performance of EPLDs and the high resource utilization of gate arrays.
Table 1 describes the highlights of the FLEX 8000 device family.
| Table 1. FLEX 8000 Highlights |
| Feature |
Benefit |
| Multivolt™ I/O operation: 5.0 V and 3.3 V |
Ideal for mixed-voltage systems |
| PCI compliance |
Meets all specifications of the PCI local bus |
| FastTrack® Interconnect routing structure: fast, continuous row and column channels along length and width of device |
Fast, predictable interconnect delays |
| JTAG compliance |
Enables in-depth board-and system-level testing |
With the FLEX 8000 family, you can easily implement applications that require high flipflop counts—such as pipelined data paths and data transformation/compression algorithms—without sacrificing fast system clock rates. PCI-compliant FLEX 8000 devices are ideal for data-intensive applications such as graphics controllers, multimedia cards, networking cards, and communications equipment. Plus, the low standby power consumption of FLEX 8000 devices makes them well-suited for use in PC add-on cards and battery-powered instrumentation.
Table 2 shows the features of the FLEX 8000 product family.
| Table 2. FLEX 8000 Product Family |
| Feature |
EPF8282A
EPF8282AV |
EPF8452A |
EPF8636A |
EPF8820A |
EPF81188A |
EPF81500A |
| Usable gates |
2,500 |
4,000 |
6,000 |
8,000 |
12,000 |
16,000 |
| Flipflops |
282 |
452 |
636 |
820 |
1,188 |
1,500 |
| Logic array blocks (LABs) |
26 |
42 |
63 |
84 |
126 |
162 |
| Logic elements |
208 |
336 |
504 |
672 |
1,008 |
1,296 |
| Maximum user I/O pins |
78 |
120 |
136 |
152 |
184 |
208 |
| JTAG BST circuitry |
Yes |
No |
Yes |
Yes |
No |
Yes |
The FLEX 8000 architecture consists of silicon-efficient, fine-grained logic elements grouped into high-performance, coarse-grained LABs. This dual granularity enables the FLEX 8000 family to offer both the fast performance of EPLDs and the high resource utilization of gate arrays.
LABs are connected through Altera's FastTrack Interconnect, a three-dimensional, programmable interconnect structure. Based on continuous row and column interconnect lines, the patented FastTrack Interconnect eliminates the highly variable, cumulative delays typical of two-dimensional, segmented FPGA interconnect structures. FLEX 8000 devices offer signal delays of only 8ns between the most widely separated logic elements—a substantial improvement over FPGA delays.
Each logic element in a FLEX 8000 device implements both registered and combinatorial logic operations. LEs contain a programmable flipflop, a 4-input LUT, and high-speed cascade- and carry-chain logic. The cascade chain allows the inputs from several logic elements to be grouped together for high fan-in logic functions with a delay of less than 1ns per stage. The carry chain allows implementation of very fast counter and adder functions for optimum system performance.
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