The HardCopy® system development methodology delivers the lowest total cost and lowest system risk of all design methodologies. The joint development between TSMC and Altera delivers pre-built-in design for manufacturability, design for yield, and reliability. The HardCopy back-end flow delivers Altera-inserted design-for-test, including stuck-at fault coverage, delay fault coverage, memory test, and JTAG-enabled I/O tests.
HardCopy series devices enable:
- Fast time-to-market and fast time-to-profit
- True hardware/software co-design delivers systems sooner.
- Stratix® series FPGA systems can be used for market testing or initial production.
- HardCopy Design Center seamlessly creates pre-qualified, fully tested production-quality samples in 8 to 12 weeks using Altera's HardCopy turnkey process.
- Lowest risk and lowest total cost
- HardCopy device design flow ensures that HardCopy devices have the same functions and intellectual property (IP) as the prototyping FPGA. Therefore no time/effort needed to "convert" design.
- HardCopy methodology enables FPGA-based systems for market validation to ensure proper features/capabilities prior to HardCopy ASIC release.
- Smaller development team, less overall hardware and software engineering time, and lower EDA tool cost result in lowest total cost.
- Lower power, increased single event upset (SEU) immunity, and increased security
