Nios II Processor Implementation in HardCopy II ASICs
The Nios® II family of embedded processors delivers three processor cores to address a wide range of embedded processing applications. These soft intellectual property (IP) processor cores can be implemented in any of the latest generations of Altera® FPGAs as well as in the HardCopy® series ASICs. you can choose from a high-performance core, a low-cost core, and a performance-/cost-balanced standard core. The Nios II family of processors addresses tasks such as:
- Acting as a system processor running a real-time operating system
- Implementing complex state machines
- Off-loading existing processors
- Performing I/O pin and data-processing tasks
- Accelerating digital signal processing (DSP) algorithms
When implemented in a HardCopy II ASIC, the Nios II embedded processor offers unparalleled processing power to meet the needs of a high-performance system on a chip (SOC). The Nios II embedded processor is capable of providing system-level processor performance, allowing the integration of the processor and system functionality and logic into a single device. HardCopy II ASICs and Nios II embedded processors, when combined, can satisfy the needs of computing, mass storage, telecommunications, and networking applications.
Figure 1 shows an example of multiple Nios II processors within a single HardCopy II ASIC in a data processing and movement application.
Figure 1. Nios II Processors in HardCopy II ASIC for Data Processing
The design flow for HardCopy devices allows you to test and verify your designs in an FPGA. The proven design is then passed to the HardCopy Design Center in a risk-free seamless migration process, to be implemented in a HardCopy ASIC. HardCopy ASICs are the only available devices in which hardware functionality can be verified in an FPGA and system software can be designed and tested in the exact system configuration, all before production.
As designs are tested in an FPGA prior to design hand-over to Altera, Altera guarantees fully working silicon from the first prototypes.
HardCopy II ASIC Architecture
HardCopy II ASICs are based on the Stratix II family of FPGAs, with various prototyping options between the HardCopy II ASIC and Stratix II FPGA. These are dependant on the required HardCopy ASIC, I/O pins, and packaging options. HardCopy II ASICs feature up to 350-MHz performance, providing the highest performance from a Nios II processor core to date, and consume only half the power of the Stratix II device used for prototyping.
The embedded digital signal processing (DSP) blocks in the Stratix II device architecture are available in HardCopy II ASICs. These DSP blocks provide the perfect complement to Nios II custom instructions and other hardware acceleration units. You can now create DSP algorithms and complex math routines in high-performance hardware DSP blocks and access them as regular software routines or implement them as custom instructions to the Nios II CPU. This gives you the flexibility and portability of high-level software design while maintaining the performance benefits of parallel hardware operations in HardCopy ASICs, and without resorting to excessive clock speeds.
The memory in a HardCopy II ASIC caters to all the memory needs of a typical SOC. Each of up to 9 M-RAM blocks offers a 64-Kbyte segment. The largest HardCopy II ASIC includes 576 Kbytes of code and data storage memory. HardCopy II ASICs also support high-speed memory interfaces to allow the use of the latest DDR2 SDRAMs for external code and data storage.
Low-Cost Licensing Model
The Nios II family of embedded processors is licensed through a one-time payment with no additional per-device or per-project royalties. As the Nios II license allows the processor core to be used in any Altera device, using Nios II processors and HardCopy II ASICs provides a cost-effective solution for high-volume production.
The Nios II license is most commonly purchased as a part of a Nios II development kit. Currently available for Stratix®, Stratix II, and Cyclone® device families, the development kits include the Quartus® II design software and Nios II Integrated Development Environment as well as a full Nios II license. All kits also include a development board and all necessary cabling and power supplies to get you designing with Nios II processors in a matter of minutes from opening the box.
Complete SOPC Solution
Altera's SOPC Builder automated system development tool provides you with a powerful platform for composing bus-based systems out of common system components such as processors, peripherals, and memory interfaces.
The HardCopy II design flow benefits from the use of the SOPC Builder block-based design methodology in the generation of the FPGA design files during the FPGA prototyping phase. The block-based design methodology aids the integration of Nios II processors and other intellectual property (IP) blocks with custom logic, custom instructions, and hardware accelerators, all of which are typical components of a high-density logic design.
The Nios II peripherals and interfaces library web page has more details on the peripherals available for the Nios II processors.
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