HardCopy II ASICs: Technology for Business
HardCopy II ASICs deliver the lowest risk, lowest total cost, fastest time-to-market, and fastest time-to-profit solution for your custom logic needs.
HardCopy II ASICs enable you to:
- Use true software/hardware co-design
- Get products to market six to nine months earlier than standard methodologies
- Create new products at a fraction of the traditional development cost
- Market and field test using Stratix® II FPGAs before committing to ASIC silicon
- Introduce multiple product variations, customized to different market needs, at the same time
The HardCopy methodology allows you to seamlessly prototype your system with Stratix II FPGAs and completely prepare your system for production, prior to ASIC design handoff. Altera’s HardCopy Design Center uses a proven turnkey process to implement the low-cost, low-power, functionally-equivalent, pin-compatible HardCopy II device. This methodology is more than just a fast ASIC development methodology, it is the ultimate system development methodology.
Built to Enable Seamless Prototyping
HardCopy II ASICs are built from the ground-up to enable Stratix II FPGA-based seamless prototyping. First, base members of the HardCopy II family are defined by using Stratix II-compatible I/O module rings. Then, the base dies are embedded with equivalent hard intellectual property (IP) blocks—such as I/O buffers, clock networks, phase-locked loops (PLLs), and memory blocks—from Stratix II FPGAs. The remaining die area is filled with proven, fine-grained HCells for logic. The result is an ASIC that is a seamless drop-in replacement to the prototyping FPGA on your system board.
More System Integration
HardCopy II ASICs are built to enable more system integration with increased capabilities:
- 90-nm technology with two-layer metal customization
- Over 350-MHz system performance
- Density improvements
- 1M to 3.6M usable ASIC gates (not including I/Os, PLLs, and built-in test logic)
- .86 Mbit to 8.6 Mbit on-chip memory
- 4 to 8 PLLs
- Typical 50 percent power reduction from the Stratix II FPGA prototype
- Low power consumption (Stratix II device family leads the FPGA industry in low power consumption)
- Application and cost-optimized packaging
- Wire bond
- High-performance flip chip
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