Getting Started with HardCopy III ASIC Designs
The strength of the HardCopy® methodology is Altera's premier Quartus® II development software suite and FPGA-based front-end seamless prototyping design process. You start your HardCopy III ASIC design by targeting the design to the appropriate Stratix® III FPGA in the latest Quartus II design software. The class-leading, high-performance, high-density, and low-power Stratix III FPGAs are available now for immediate prototyping needs.
Quartus II software is the industry’s only true "design-once" development tool that allows you to use one register transfer level (RTL) and one intellectual property (IP) set for two device implementations. As shown in Table 1, Quartus II software offers a highly integrated, complete front-end design environment from design entry to HardCopy ASIC netlist handoff. Native synopsys design constraint (.sdc) support in Quartus II software not only provides accurate synthesis and static timing analysis, but also offers total compatibility to the back-end design tools such as Synopsys PrimeTime.
| Table 1. HardCopy ASIC Feature Support in Quartus II Software |
| Feature |
Description |
| RTL Synthesis |
Quartus II Integrated Synthesis (QIS) provides broad HDL language, advanced synthesis options, and compiler directives (attributes) to achieve optimal results. |
| Physical Synthesis |
Enables quicker timing closure and allows higher performance for the HardCopy III device over its prototyping Stratix III device. |
| Simulation |
ModelSim®-Altera® tool supports behavioral simulation and VHDL or Verilog testbenches. |
| Static Timing Analysis |
Use TimeQuest timing analyzer to perform synopsys design constraint-based static timing analysis and achieve timing closure prior to design handoff. |
| Place and Route |
Performs detailed placement and global routing for tight timing correlation to the back-end final timing results. |
| Incremental Compile |
Reduces design compilation times up to 70 percent and improves timing closure by allowing you to target design optimization within individual design partitions, while leaving other regions untouched. |
| Formal Verification |
Built-in equivalence checking to compare HardCopy gate-level netlist file with FPGA netlist. Also supports RTL to netlist equivalence check using Cadence Conformal software. |
| Pin Planning |
Assign pin-out and verify the legality of pin assignments. |
| Power Estimation |
PowerPlay power analysis and optimization technology helps you effectively manage power from design concept through implementation. |
| SOPC Builder |
Enables you to rapidly and easily build systems and evaluate embedded systems. |
| Nios II IDE |
Integrated design environment for the industry's most popular configurable Nios® II embedded processors. |
| HardCopy Advisor |
Provides development guidelines for successful design handoff to Altera's HardCopy Design Center. It reports the tasks completed and those you still need to complete. |
Altera offers these resources to get you started designing with HardCopy III ASICs:
For further details, contact your local Altera sales office, representative, or distributor.
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