HardCopy III ASIC Architecture
HardCopy® III ASICs are built from the ground-up to enable Stratix® III FPGA-based seamless prototyping. First, base members of the HardCopy III family are defined by using Stratix III-compatible I/O module rings. Then, the base dies are embedded with equivalent hard intellectual property (IP) blocks, such as I/O buffers, clock networks, phase-locked loops (PLLs), DLLs, and M9K and M144K memory blocks, from Stratix III FPGAs. The remaining die area is filled with proven, fine-grained HCells for logic, digital signal processing (DSP) functions, and distributed MLAB memories. The result is an ASIC that is interchangeable with a Stratix III FPGA on your system board. Figure 1 shows the HardCopy III architecture.
Figure 1. HardCopy III ASIC Architecture
Altera’s Quartus® II development software offers the industry’s only “design-once” tool for both HardCopy ASICs and prototyping FPGAs. You use one register transfer level (RTL) design, one set of timing constraints, one IP set, and one design tool for two device implementations. Furthermore, design-for-test, design-for-manufacturing, and design-for-yield are pre-built into the base layer and metal structures of the HardCopy silicon. There is no need for you to spend time and money on any design for test, design for manufacturability, and design for yield activities. The result is an ASIC with the lowest risk and lowest total cost that also provides the benefit of faster time-to-market and time-to-profit.
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