The HardCopy® III ASIC family delivers low-risk, low-total-cost, fast time-to-market, and fast time-to-profit solutions for your custom logic needs. If your application calls for lower material costs, reduced power, increased performance, single event upset (SEU) immunity, security, or any combination of these requirements, look to HardCopy ASICs.
Table 1 shows the HardCopy III ASIC family. Table 2 shows the industrial temperature support for HardCopy III ASICs and Table 3 shows the extended temperature support for HardCopy III ASICs.
Get product family details: HardCopy III ASIC Product Table (PDF).
Full-featured HardCopy III ASICs offer high logic density, high memory count, and flexible high-performance I/Os. They are seamlessly prototyped using interchangeable high-performance Stratix® III FPGAs. These HardCopy III ASICs are suitable for communications, test and measurement, medical, computer, storage, avionics, and military market applications that require the highest performance and direct socket replacement for the prototyping FPGAs. Full-featured HardCopy III ASICs are typically in the performance-optimized flip-chip packages.
Cost-optimized HardCopy III ASICs offer optimized memory, performance, I/Os, and package to their prototyping Stratix III FPGAs. These HardCopy III ASICs are a good fit for cost-sensitive wireless, printing, and automotive market applications. These are applications that may not require the highest possible performance, or can benefit from a board re-spin to take advantage of a much lower cost ASIC. HardCopy III ASICs are typically in the cost-optimized flip-chip or wire-bond packages.
| Table 1. HardCopy III ASIC Family Overview | |||||||||
| Device | Packages (1) | FPGA Prototype |
I/O Pins | Embedded Memory (Kb) (2) | PLLs | Usable ASIC Gates (3) | |||
|---|---|---|---|---|---|---|---|---|---|
| F484 | F780 | F1152 | F1517 | ||||||
| HC325 | W,F | W,F | EP3SL110 EP3SL150 EP3SE110 EP3SL200 EP3SL260 EP3SL340 |
488 | 12,384 | 4 | 7.0M | ||
| HC335 | F | F | EP3SL150 EP3SE110 EP3SL200 EP3SL260 EP3SL340 |
880 | 16,272 | 12 | 7.0M | ||
- W = wire bond, F = performance-optimized flip chip, L = cost-optimized flip chip
- Memory bit count does not include the distributed memory logic array blocks (MLABs), which are implemented in HCells
- ASIC gates calculated as 12 gates per logic element (LE), 5,000 gates per 18x18 multiplier. Gate count does not include RAMs, phase-locked loops (PLLs), test circuitry, and I/O registers.
| Table 2. HardCopy III ASIC Industrial Temperature Support (-40°C to 100°C) | |
| Device | Package |
|---|---|
| HardCopy III | All |
| Table 3. HardCopy III ASIC Extended Temperature Support (-40°C to 125°C) | |
| Device | Package |
|---|---|
| HardCopy III | All |
