Don't think low development cost OR fast time-to-market—think low development cost AND fast time-to-market. Don't compromise. Think HardCopy® IV ASICs.
Altera® HardCopy IV ASICs deliver the lowest total cost, lowest risk, AND fastest time-to-market, fastest time-to-profit solution for your custom logic needs.
With up to 36 transceivers, 2.8M to 15M usable ASIC gates, and 6.3 Mbits to 20.3 Mbits of on-chip memory, HardCopy IV ASICs meet the requirements of a wide range of applications. HardCopy IV ASICs are available in two 40-nm variants:
- HardCopy IV GX devices focus on applications requiring high-speed transceivers
- HardCopy IV E devices focus on logic, memory, and/or digital signal processing (DSP)-rich applications
Delivering the excellent transceiver performance and signal integrity you've come to expect from Altera, HardCopy IV GX devices contain up to 36 transceivers, up to 11.5M ASIC gates, and up to 20.3 Mbits of on-chip memory. High-reliability computing, storage, military, and, of course, wireless and wireline markets all have ideal applications for these high-speed transceiver ASICs.
HardCopy IV E devices contain up to 15M ASIC gates and up to 18.4 Mbits of on-chip memory. These devices support wire-bond packaging in addition to flip-chip packages.
Benefits of ASICs and FPGAs
- One design, one register transfer level (RTL), one IP set, and one tool (Quartus® II software) deliver both FPGA and ASIC implementations
The methodology you use to create HardCopy ASICs allows you to seamlessly prototype your system with Stratix® IV FPGAs and completely prepare your system for production, prior to ASIC design handoff. Altera's HardCopy Design Center uses a proven turnkey process to implement low-cost, low-power, functionally-equivalent, pin-compatible HardCopy IV devices. This methodology is more than just a fast ASIC development methodology, it is the ultimate system development methodology.
Lowest risk and lowest total cost
Working in partnership with Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has proven to be very beneficial in the production of high yielding, highly manufacturable, and highly reliable HardCopy IV ASICs. All the building blocks are validated via a series of test chips, including transceivers, I/Os, phase-locked loops (PLLs), and SRAMs. The transceivers and other intellectual property (IP) blocks are identical between Stratix IV FPGAs and HardCopy IV ASICs. All test insertion and test program generation is performed during the HardCopy back-end process, delivering excellent stuck-at fault and delay fault coverage. As a result, Altera delivers the lowest risk approach for deep sub-micron ASICs.
Using our system development methodology can cut 9 to 12 months from a typical hardware and software system design. This system development methodology, coupled with the elimination of all design-for-test, design-for-manufacturability, and design-for-yield tools and time, dramatically reduces your engineering expenses. These reductions, coupled with low NRE, deliver the lowest total cost.
Higher levels of system integration and innovation
- Transceivers
- Up to 36 6.5+ Gbps channels
- Density
- 2.8M to 15M usable ASIC gates (not including transceiver hard IP, I/Os, PLLs, and built-in test logic)
- 6.3 Mbits to 20.3 Mbits on-chip memory
- 2 to 12 PLLs
- Power
- Competitive with standard-cell ASIC solutions
- Typical 50 percent power reduction from the Stratix IV FPGA prototype
- Stratix IV device family leads the FPGA industry in low power consumption for high-end FPGAs
- Application optimized packaging
- Wire bond
- Cost-optimized flip chip
- Performance-optimized flip chip
- Intellectual property
- Altera and our partners offer a wide variety of silicon-proven IP
- Allows you to focus on your differentiating technology without re-inventing already available IP
With Altera at 40 nm, it's not about sacrificing one benefit to gain another. Go ahead, innovate without compromise—think AND, not OR.
