HardCopy IV ASICs Family Overview
HardCopy® IV ASICs deliver low risk, low total cost, and fast time-to-market/fast time-to-profit solutions for your custom logic needs. If your applications require any combination of reduced power, lower BOM cost, increased performance, single event upset (SEU) immunity, instant-on capability, or increased security, HardCopy IV ASICs are for you.
Now available with transceivers, HardCopy IV GX device variants support an even wider range of applications. Application examples requiring a high-speed serializer/deserializer (SERDES) interface include:
- Wireline
- Bridging/translation applications
- Endpoint functions for GPON and enterprise routers
- Computer and storage functions requiring high levels of SEU tolerance
- Wireless basestations requiring low power and large digital signal processing (DSP) capability
HardCopy IV E device variants have all the capabilities of HardCopy ASICs, but without transceivers.
See the HardCopy IV end-market and applications page for additional information.
Tables 1 and 2 provide details on the HardCopy IV ASIC family. For additional information, see the product catalog (PDF).
| Table 1. HardCopy IV GX Devices Overview |
| Device (1) |
ASIC Gates
(2) |
Memory
Bits
(3) |
6.5+ Gbps SERDES |
I/O Pins |
Phase-
Locked
Loops (PLLs) |
Hardware
Interoperability
Platforms
(HIPs) |
FPGA Prototype |
| HC4GX1YZ |
2.8M |
6.3 |
4/8 |
200 - 368 |
3 |
1 |
EP4SGX70 |
| HC4GX2YZ |
3.9M |
8.1 |
4/8/16 |
200 - 368 |
3/4 |
1/2 |
EP4SGX110 |
| HC4GX3YZ |
9.2M |
9.8 - 12.2 |
4/8/16/24 |
200 - 736 |
3/6/8 |
1/2 |
EP4SGX230 |
| HC4GX4YZ |
7.6M |
10.6 - 12.7 |
16/24 |
256 - 736 |
3/6/8 |
2 |
EP4SGX290 |
| HC4GX5YZ |
9.5M |
10.6 - 13.3 |
16/24 |
256 - 736 |
3/6/8 |
2 |
EP4SGX360 |
| HC4GX6YZ |
11.5M |
13.3 |
24 |
560 - 736 |
6/8 |
2 |
EP4SGX530 |
| Table 2. HardCopy IV E Devices Overview |
| Device (1) |
ASIC
Gates
(2) |
Memory
Bits
(3) |
I/O Pins |
PLLs |
FPGA
Prototype |
| HC4E2YZ |
3.9M |
8.1 |
296 - 480 |
4 |
EP4SE110 |
| HC4E3YZ |
9.2M |
10.7 |
296 - 480 |
4 |
EP4SE230 |
| HC4E4YZ |
7.6M |
12.1 - 13.3 |
392 - 864 |
4/8/12 |
EP4SE290 |
| HC4E5YZ |
9.5M |
16.8 |
480 - 864 |
4/8/12 |
EP4SE360 |
| HC4E6YZ |
11.5M |
16.8 |
736 - 880 |
8/12 |
EP4SE530 |
| HC4E7YZ |
13.3M |
16.8 |
736 - 880 |
8/12 |
EP4SE680 |
Notes:
- Y = I/O count, Z = package type (see the product catalog for more information)
- ASIC gates calculated as 12 gates per logic element (LE), 5,000 gates per 18 x 18 multiplier
(SRAMs, PLLs, test circuitry, I/O registers not included in gate count)
- Not including MLABs
The Benefits of FPGAs AND the Benefits of ASICs
The HardCopy methodology allows you to seamlessly prototype your system with Stratix® IV FPGAs to completely prepare it for production, prior to ASIC design handoff. Altera's HardCopy Design Center uses a proven turnkey process to implement the lower-cost, lower-power, functionally-equivalent, pin-compatible HardCopy IV ASICs. This methodology provides more than just a fast ASIC development, it is the ultimate system development methodology.
HardCopy system development methodology allows you to do one design, using one methodology, one tool, and one company, and then ramp production when it makes sense for your market. No other company can offer you a lower risk alternative or faster development.
For additional technical information, see the Stratix IV Device Handbook. For additional information about the benefits of HardCopy IV ASICs, see the HardCopy IV power, HardCopy IV SEU, or HardCopy IV performance web pages.
To get started with your designs, see the HardCopy IV Getting Started web page.
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