HardCopy® IV ASICs deliver low risk, low total cost, fast time-to-market, and fast time-to-profit solutions for your custom logic needs. If your applications call for reduced power, lower BOM cost, increased performance, single event upset (SEU) immunity, instant-on capability, increased security, or any combination of these requirements, HardCopy IV ASICs are for you.
Now available with transceivers, HardCopy IV GX devices support an even wider range of applications. Application examples requiring a high-speed serializer/deserializer (SERDES) interface include:
- Wireline
- Bridging/translation applications
- Endpoint functions for GPON and enterprise routers
- Computer and storage functions requiring high levels of SEU tolerance
- Wireless basestations requiring low power and large digital signal processing (DSP) capability
HardCopy IV E ASICs have all the capabilities of HardCopy IV GX ASICs, but without transceivers.
See the HardCopy IV ASICs End Markets and Applications page for additional information.
Tables 1 and 2 provide details on the HardCopy IV ASIC family. For additional information, see the HardCopy IV Handbook.
| Table 1. HardCopy IV GX Devices Overview | |||||||
| Device (1) | ASIC Gates (2) |
Memory Bits (3) |
6.5+ Gbps SERDES | I/O Pins | Phase- Locked Loops (PLLs) |
Hardware Interoperability Platforms (HIPs) |
FPGA Prototype |
|---|---|---|---|---|---|---|---|
| HC4GX15 | 9.4 M | 9.2 Mb | 8 | 372 | 3 | 1 |
EP4SGX70 |
| HC4GX25 | 11.5 M | 13.3 Mb | 24 | 564 | 6 | 2 |
EP4SGX110 |
| HC4GX35 | 11.5 M | 20.3 Mb | 36 | 744 | 8 | 2 |
EP4SGX180 |
| Table 2. HardCopy IV E Devices Overview | |||||
| Device | ASIC Gates (1) |
Memory Bits (2) |
I/O Pins | PLLs | FPGA Prototype |
|---|---|---|---|---|---|
| HC4E25 | 9.4 M | 12.1 Mb | 488 | 4 | EP4SE230 EP4SE360 |
| HC4E35 | 15 M | 18.4 Mb | 880 | 12 |
EP4SE360 |
Notes:
- ASIC gates are calculated as 12 gates per logic element (LE), 5,000 gates per 18x18 multiplier
(SRAMs, PLLs, test circuitry, I/O registers not included in gate count) - Not including MLABs
Altera provides industrial temperature support for all HardCopy IV devices.
The Benefits of FPGAs and the Benefits of ASICs
The HardCopy methodology allows you to seamlessly prototype your system with Stratix® IV FPGAs to completely prepare it for production, prior to ASIC design handoff. Altera's HardCopy Design Center uses a proven turnkey process to implement the lower-cost, lower-power, functionally-equivalent, pin-compatible HardCopy IV ASICs. This methodology provides more than just a fast ASIC development, it is the ultimate system development methodology.
HardCopy system development methodology allows you to do one design, using one methodology, one tool, and one company, and then ramp production when it makes sense for your market. No other company can offer you a lower risk alternative or faster development.
For additional technical information, see the Stratix IV Device Handbook. For additional information about the benefits of HardCopy IV ASICs, see the HardCopy IV Power Advantage, High SEU Tolerance, or Improved Performance web pages.
To get started with your designs, see the HardCopy IV Getting Started web page.
