HardCopy® Stratix® devices offer the same system-level features as Stratix FPGAs. More details on the architecture and the features offered in Stratix FPGAs are available on the Stratix home page.
Table 1 highlights the differences between Stratix FPGAs and HardCopy Stratix devices. The Stratix Overview page and the HardCopy Stratix Overview page have details on family members and packaging options.
| Table 1. HardCopy Stratix & Stratix FPGA Comparison | ||
| Feature | Functionality | |
|---|---|---|
| Stratix FPGA | HardCopy Stratix Device | |
| TriMatrix Memory | Up to 7 Mbits of TriMatrix memory | Up to 5.6 Mbits of TriMatrix memory |
| External Memory Interfaces | External memory interface to high-density SRAM and DRAM devices | Identical |
| SRAM Device Interface | Support for double data rate (DDR), quad data rate (QDR), QDRII, and zero-bus turnaround (ZBT) SRAM devices with clock speeds up to 200 MHz | Identical |
| DRAM Device Interface | Support for single data rate (SDR SDRAM), DDR SDRAM, and fast-cycle (FCRAM) with clock speeds up to 200 MHz | Identical |
| Digital Signal Processing (DSP) Blocks | Up to 22 DSP blocks | Identical |
| DSP Performance | Up to 463 giga multiply-accumulate operations per second (GMACS) of DSP throughput | Identical |
| High I/O Bandwidth | Support for a variety of single-ended and differential I/O standards | Identical |
| Differential I/O Support | Up to 152 high-speed differential I/O channels with 80 channels optimized for data rates up to 840 Mbps, and support for emerging I/O interfaces including the LVDS, LVPECL, PCML, and HyperTransport™ standards | Identical |
| Single-Ended I/O Support | Support for high-bandwidth single-ended I/O interface standards, such as SSTL, HSTL, GTL, GTL+, CTT, and PCI-X | Identical |
| High-Speed Interfaces | Support for a wide array of high-speed interface standards, such as the SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, HyperTransport, RapidIO®, and UTOPIA IV standards | Identical |
| Clock Management Circuitry | Support for up to 12 programmable phase-locked loops (PLLs) and 40 system clocks | Identical |
| Clock Management Features | Several advanced clock management features including clock switchover, PLL reconfiguration, spread-spectrum clocking, frequency synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth | Identical |
| On-Chip Termination | Support for differential on-chip termination | Identical |
| Remote System Upgrades | Support for remote system upgrades | Identical |
| Nios® II Embedded Processors | Support for the Nios® II soft embedded processor that offers overall system performance over 200 Dhrystone MIPS (DMIPS) | Identical |
| Embedded Test Capability | Not Available | Available |
| Configuration Emulation | Not Available | Available |
