Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature

High-End FPGAs       About Stratix Series    Stratix IV (E and GX)    Stratix III (L and E)    Stratix II (and GX)    Stratix (and GX)     Midrange FPGAs    Arria (GX)     Low-Cost FPGAs    Cyclone III    Cyclone II    Cyclone     CPLDs    MAX II (and G, Z)    MAX 3000A     ASICs       About HardCopy Series    HardCopy IV (E and GX)    HardCopy III    HardCopy II    HardCopy Stratix           Overview           Design Utilities           Features           Literature     Device-Specific Offerings    RoHS Compliant       Extended Temperature       Industrial Temperature       Military Temperature       Automotive Temperature     Configuration Devices    Enhanced Configuration    Serial Configuration     Mature Products       Product Listing

Home > Products > Devices > HardCopy Stratix > Overview Print This Page Subscribe to Email HardCopy Stratix ASIC Overview Derived from the Stratix® FPGA architecture, HardCopy® Stratix devices offer a seamless migration path to high-volume, low-cost ASICs. On average, HardCopy Stratix devices boost performance by 50 percent and reduce power consumption by 40 percent compared to the Stratix FPGA. HardCopy Stratix devices are fully supported within the Quartus® II design software, offering the industry's first and only unified design flow from FPGA prototype to high-volume ASICs. The Quartus II software also provides both power and performance estimates for HardCopy Stratix devices, allowing for accurate, up-front design performance estimation and smooth design flow. Tables 1 and 2 outline the HardCopy Stratix device family features, I/O pin counts, and package options. Table 1. HardCopy Stratix Device Overview Feature HC1S25 HC1S30 HC1S40 HC1S60 HC1S80 Logic Elements (LEs) 25,660 32,470 41,250 57,120 79,040 M512 RAM Blocks (512 Bits + Parity) 224 295 384 574 767 M4K RAM Blocks (4 Kbits + Parity) 138 171 183 292 364 M-RAM Blocks (512 Kbits + Parity) 2 2 (1) 2 (1) 6 6 (1) Total RAM bits 1,944,576 2,137,536 2,244,096 5,215,104 5,658,048 Digital Signal Processing (DSP) Blocks 10 12 14 18 22 Embedded Multipliers (2) 80 96 112 144 176 Phase-Locked Loops (PLLs) 6 6 6 12 12 Maximum user I/O pins 473 597 615 773 773 Notes: The number of M-RAM blocks in this device differs from the number of M-RAM blocks in the corresponding Stratix FPGA. Total number of 9 x 9 multipliers. To obtain the total number of 18 x 18 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 2. To obtain the total number of 36 x 36 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 8. Table 2. HardCopy Stratix Device User I/O Pins and Package Options Package Size (mm x mm) HC1S25 HC1S30 HC1S40 HC1S60 HC1S80 672-Pin FineLine BGA 27 x 27 473 780-Pin FineLine BGA 29 x 29 597 615 1,020-Pin FineLine BGA 33 x 33 773 773 Rate This Page   Related Links HardCopy Stratix Devices HardCopy Stratix Features HardCopy ASICs

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Devices | Design Software | Intellectual Property | Design Services | Dev. Kits/Cables | Literature  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation