HardCopy Seamless Migration Process
Altera's HardCopy® structured ASICs give you a design process with the flexibility of FPGAs and the low cost of ASICs for your high-volume applications. Develop your design and test it in-system with an Altera® FPGA. When your design is fully tested to meet your requirements, the Altera HardCopy Design Center migrates the design to a functionally equivalent, pin-compatible HardCopy device. You get:
- A complete production solution, from prototype to high volume
- Devices, tools, and intellectual property (IP)
- Single vendor from prototype to production
- Minimal design risk and guaranteed functionality
- FPGA-proven functionality preserved—netlist is unchanged
- Proven process technology (same as the FPGA)
- Same package and pin-outs as the FPGA
- Fast device turnaround
- Minimal effort during the migration process
Figure 1 shows the simple set of "single-click" deliverables for migrating an FPGA design to a HardCopy structured ASIC.
Figure 1. HardCopy Migration Process
The Altera HardCopy Design Center migrates your FPGA design by:
- Generating a Verilog structural netlist from the functionally proven FPGA design file and ensuring it adheres to industry-standard design-for-testability (DFT) rules
- Creating an optimized layout of the design using the placement and timing constraints provided in the deliverables
- Verifying that the design satisfies timing requirements (the design's migration and verification is complete in two to four weeks)
- Manufacturing prototypes using the same fab and process technology used for the FPGA
Volume production starts once you have approved the prototypes for satisfactory functionality. Devices are ready for shipment eight weeks later.
You get production devices in approximately 20 weeks (see Figure 2) from Altera's acceptance of the FPGA design database. Most customers use FPGAs for production until HardCopy production devices are shipped.
Figure 2. HardCopy Implementation Timeline
HardCopy NRE costs ranges from:
- $165K to $210K for 130-nm HardCopy Stratix® devices
- $240K to $345K for 90-nm HardCopy II devices
The HardCopy solution offers a unique value because it is a turnkey migration. The Altera HardCopy Design Center migrates an FPGA design to a HardCopy structured ASIC without the effort traditionally required when using an alternative ASIC:
- No additional effort for ASIC timing closure. HardCopy device timing closure placement is prepared by the Quartus® II software fitter
- No time spent on logic verification and simulation after the FPGA design is completed
- No DFT logic to insert or test vectors to generate
- No required purchase of additional software tools
- No required board re-spins
- Guaranteed pin-compatible and functionally equivalent to the Stratix series FPGA in which the design was developed and tested
Altera's seamless migration process has been employed in numerous design migrations resulting in successful HardCopy structured ASICs. All prototypes were delivered to the customers as per the above timeline and are currently in volume production.
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