HardCopy Silicon Technology
Altera's HardCopy® series of structured ASICs consist of a common set of base arrays with the top-level metal layers reserved for your unique design, delivering quick turnaround.
The HardCopy series offers the lowest-risk structured ASICs because you develop and verify your design in an FPGA before migrating it to a guaranteed, functionally-equivalent HardCopy device.
Using HardCopy structured ASICs, you get the density, performance, and cost of advanced ASIC technology with the flexibility of an FPGA design flow. Only Altera can offer this capability.
HardCopy Process Technology Matches Equivalent FPGA
The three-generation HardCopy series—HardCopy II, HardCopy Stratix, and HardCopy APEX devices—are developed in the same qualified process technology and process voltage as their equivalent FPGAs (see Table 1). The migration process is no-risk because the FPGAs are rigorously tested, mass produced, and shipped in volume before their equivalent HardCopy series devices are fabricated, thus maximizing first-time success and meeting customers' time-to-market demands.
| Table 1. HardCopy Series Process Technologies |
|
Device Family
|
HardCopy Process Technology |
Number of Customizable Layers |
Voltage (Same as FPGA) |
FPGA Process Technology |
| HardCopy II |
90 nm
|
2 |
1.2 |
90 nm |
| HardCopy Stratix |
0.13 µm |
2 |
1.5 |
0.13 µm |
| HardCopy APEX 20KC |
0.18 µm (Al) |
3 |
1.8 |
0.15 µm
all-layer copper |
| HardCopy APEX 20KE |
0.18 µm (Al) |
3 |
1.8 |
0.18 µm (Al) |
HardCopy Series Reduces Development Time & Cost
HardCopy series structured ASICs use a common base layer that contains the logic, hard intellectual property (IP)—such as memory, I/O pins, and phase-locked loops (PLLs)—routing, and power busing (see Figure 1). The device is customized using the top metal layers.
Figure 1- Difference Between Standard-Cell & Structured ASIC Technology
HardCopy structured ASICs offer much lower non-recurring engineering (NRE) costs, faster turn-around, and lower risk compared to standard-cell ASICs:
- Only the top metal layers have to be generated, reducing engineering time and costs
- The base layers are pre-engineered, verified, and characterized. All deep sub-micron effects are resolved.
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