HardCopy III ASIC Family Overview
HardCopy® III ASICs deliver low risk, low total cost, and fast time-to-market and time-to-profit solutions for your custom logic needs. If your application requires any combination of lower BOM cost, reduced power, increased performance, SEU immunity, and security, HardCopy ASICs are for you.
The HardCopy methodology allows you to seamlessly prototype your system with Stratix® III FPGAs and completely prepare your system for production, prior to ASIC design handoff. Altera’s HardCopy Design Center uses a proven turnkey process to implement the low-cost, low-power, and functionally-equivalent HardCopy III device. This methodology is more than just a fast ASIC development methodology, it is the ultimate system development methodology.
The HardCopy III ASIC family is built to enable a variety of applications by offering a wide breadth of logic, memory, IO, and package combinations from full-featured to cost-optimized. HardCopy III ASICs are available in commercial, industrial, and military temperature grades to support varying operating environments with junction temperature support from -55oC to 125oC. Table 1 shows the HardCopy III device family.
Full-featured HardCopy III ASICs offer high logic density, high memory count, and flexible high-performance I/Os. They are seamlessly prototyped using the interchangeable high-performance Stratix III FPGAs. These HardCopy III devices are suitable for applications in the communications, test and measurement, medical, computer, storage, avionics, and military markets that require highest performance and direct socket replacement for the prototyping FPGAs. Full-featured HardCopy III devices are typically in the performance-optimized flip-chip packages.
Cost-optimized HardCopy III ASICs offer optimized memory, performance, I/O, or package to their prototyping Stratix III FPGAs. These HardCopy III devices are a good fit for the wireless, printer, and automotive markets in cost-sensitive applications that may not require the highest possible performance or can benefit from a board re-spin to take advantage of a much lower cost ASIC. Cost-optimized HardCopy III devices are typically in the cost-optimized flip-chip or the lowest-cost wire bond packages.
| Table 1. HardCopy III ASIC Family |
| Device (1) |
Packages (2) |
FPGA
Prototype |
I/O Pins |
Memory Bits (3) |
PLLs |
ASIC Gates (4)
|
| F484 |
F780 |
F1152 |
F1517 |
| HC31YZ |
W,F |
W,F |
|
|
3SL110 |
296-488 |
4.2 Mbit |
4 |
2.7M |
| HC32YZ |
W,F |
W,F |
L,F |
|
3SL150 |
296-744 |
5.5 Mbit |
4/8 |
3.6M |
| HC33YZ |
W,F |
W,F |
L,F |
|
3SE110 |
296-744 |
5.5 - 8 Mbit |
4/8 |
5.8M |
| HC35YZ |
W,F |
W,F |
L,F |
|
3SL200 |
296-744 |
5.5 - 9.6 Mbit |
4/8 |
5.3M |
| HC36YZ |
W,F |
W,F |
L,F |
L,F |
3SE260 |
296-880 |
5.5 -11.3 Mbit |
4/8/12 |
6.9M |
| HC37YZ |
W,F |
W,F |
L,F |
L,F |
3SL340 |
296-880 |
11.3 -16.3 Mbit |
4/8/12 |
7.0M |
Notes:
- Y = I/O count, Z = package type (W, F, or L)
- W = Wire bond, F = Performance-optimized flip chip, L = Cost-optimized flip chip
- Memory bit count does not include the distributed MLAB memory blocks, which are implemented in HCells
- ASIC gates calculated as 12 gates per logic element (LE), 5000 gates per 18 x 18 multiplier. Gate count does not include RAMs, phase-locked loops (PLLs), test circuitry, and I/O registers.
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