|
Table 1. HardCopy II Features at a Glance
|
|
Feature
|
Description
|
|
Source- Synchronous Signaling I/O Standards
|
HardCopy II devices offer up to 116 receiver and 116 transmitter channels that support source-synchronous signaling for data transfer rates as high as 1 gigabit per second (Gbps).
|
|
Differential I/O Support
|
HardCopy II devices offer high-speed differential I/O support for data rates up to 1 Gbps and address the high-performance needs of emerging I/O interfaces, including support for the LVDS, LVPECL, and HyperTransport™ standards.
|
|
Single-Ended I/O Standards
|
HardCopy II devices support high-bandwidth, single-ended I/O interface standards (SSTL, HSTL, PCI, and PCI-X) needed for today’s demanding system requirements.
|
|
Source-Synchronous Protocols
|
HardCopy II devices support a wide array of high-speed interface standards (SPI-4.2, SFI-4, 10 Gigabit Ethernet XSBI, HyperTransport, RapidIO™, NPSI, and UTOPIA IV) for flexibility and fast time-to-market.
|
|
Memory
|
HardCopy II devices offers up to 8.8 Mbits of RAM. This advanced memory structure consists of M4K and M-RAM embedded RAM blocks that can be configured to support a wide range of features.
|
|
External Memory Interfaces
|
HardCopy II devices provide advanced external memory interfaces, allowing designers to integrate external high-density SRAM and DRAM devices into complex system designs without degrading data-access performance.
|
|
Soft Multipliers
|
HardCopy II devices provide a flexible implementation of soft multipliers that can be configured for different data width and latency. The soft multipliers provide very high DSP throughput in addition to the DSP blocks.
|
|
Clock Management Features
|
HardCopy II devices feature up to 12 programmable phase-locked loops (PLLs), providing robust clock management and frequency synthesis capabilities for maximum system performance. The PLLs provide high-end features, including clock switchover, PLL reconfiguration, spread-spectrum clocking, frequency synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth. These features allow designers to manage system timing on and off HardCopy II devices.
|
|
On-Chip Termination
|
HardCopy II devices feature series and differential on-chip termination that can simplify board layout by minimizing the number of external resistors needed on the PCB.
|
|
Nios® II Processors
|
The advanced architectural features of HardCopy II devices combined with the Nios II family of embedded processors offer unparalleled processing power to meet the needs of network, telecommunications, DSP applications, mass storage, and other high-bandwidth systems. HardCopy II devices improve overall system performance of the latest Nios II processors.
|
Literature
> 
Next Steps