HardCopy II Device Family Overview
HardCopy® II ASICs, Altera's third generation in the HardCopy series, continue to deliver low risk, low total cost, and fast time-to-market/fast time-to-profit solutions for your custom logic needs.
If your applications require any combination of reduced power, lower BOM cost, increased performance, SEU immunity, and security, HardCopy ASICs are for you.
The HardCopy methodology provides a low-risk way to prototype your system with Stratix® II FPGAs to completely prepare it for production, prior to ASIC design handoff. Altera's HardCopy Design Center uses a proven turnkey process to implement the low-cost, low-power, functionally-equivalent, pin-compatible HardCopy II device. This methodology is more than just a fast ASIC development methodology, it is the ultimate system development methodology.
This system development methodology allows you to do one design, using one methodology, one tool, and one company, and then ramp production when it makes sense for your application. No other company can offer you a lower risk alternative or faster development. Table 1 provides details on the HardCopy II family.
| Table 1. HardCopy II Family Overview |
| Device (1) |
ASIC Gates (2) |
Memory
Bits |
PLLs |
I/O Pins |
FPGA Prototype |
| HC210W |
1M |
.86Mb |
4 |
308 |
EP2S30
EP2S60
EP2S90 |
| HC210 |
1M |
.86Mb |
4 |
334 |
EP2S30
EP2S60
EP2S90 |
| HC220 |
1.9M |
3.0Mb |
4 |
492-494 |
EP2S60
EP2S90
EP2S130 |
| HC230 |
2.9M |
6.2Mb |
8 |
698 |
EP2S90
EP2S130
EP2S180 |
| HC240 |
3.6M |
8.6Mb |
4 |
742-951 |
EP2S180 |
Notes:
- W = wire bond
- ASIC gates calculated as 12 gates per LE, 5000 gates per 18 x 18 multiplier (RAMs, PLLs, test circuitry, I/O registers not included in gate count)
For additional technical information see the HardCopy Series Handbook. For additional benefits of HardCopy II ASICs, see HardCopy II power improvement, HardCopy II SEU, or HardCopy II performance.
To get started with your designs, see HardCopy II Getting Started.
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