HardCopy II ASICs: Power Advantage
HardCopy® II ASICs, like other Altera® products, are architected to deliver the best possible power for your design. To reduce leakage current, all unused blocks—RAMs, logic, and phase-locked loops (PLLs)—are removed from the power rail. For active power, the HardCopy II device's clocking circuitry and the hard-wired logic connections create a reduction in dynamic power.
Figure 1 shows the components of total power and looks at the relative values between the HardCopy II ASIC and the companion Stratix® II FPGA prototype.
Figure 1. Power Comparison
In general, as shown in Figure 1, the I/O pin power, RAM, and digital signal processing (DSP) power in the Stratix II FPGA and the HardCopy II ASIC are the same. There is a dramatic reduction in the dynamic (clock/logic) power and in leakage power because all unused elements are removed from the power rail.
HardCopy II ASICs can deliver 50 percent or greater power reduction
Benefits of Low Power Consumption
Reducing the power consumption of custom logic devices carries far-reaching benefits for many applications, including:
- Portable or handheld battery-powered devices
- Space-constrained and other thermally challenging environments
- Price-sensitive applications where cooling systems are not cost effective
The HardCopy II ASIC family is only one example of Altera’s lowest power custom logic device offerings. By combining a comprehensive approach of architecture and silicon enhancements, the latest semiconductor process technology, and complete power management tools for customers, Altera continues to lead in the delivery of excellent power technology.
Accurate Power Estimation and Analysis
Altera supports power estimation and analysis from design concept through implementation, with the most accurate and complete power management design tools. Underscoring its commitment to accuracy in power analysis, Altera is the only programmable logic vendor that offers 85°C and worst-case silicon power estimates throughout its tool suite. Altera offers the following power estimation and analysis resources:
Use the PowerPlay early power estimator during the design concept phase, and the PowerPlay power analyzer during the design implementation phase. The PowerPlay early power estimator is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization.
The PowerPlay power analyzer is a far more detailed power analysis tool that uses actual design placement, routing, and logic configuration, and can use simulated waveforms to estimate dynamic power very accurately. The power analyzer, in aggregate, usually provides ±10 percent accuracy when used with accurate design information. Quartus II PowerPlay power analysis models closely correlate to actual silicon measurements. Altera uses over 5,000 different test configurations to measure the power of individual components within a Stratix FPGA/HardCopy ASIC series device. Each configuration is focused on measuring a single circuit component of the FPGA in a specific configuration.
Quartus II Power Optimization
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area trade-offs have been automated within the register transfer level (RTL) through the place-and-route design flow. Altera has taken a leadership position in bringing power optimization into the design flow. Quartus II development software, combined with the architecture enhancements in Altera’s products, continues to deliver leading power solutions.
Quartus II software has many transparent, automatic power optimizations that utilize the architecture details to minimize power, including:
- Transforming major functional blocks
- Mapping user RAMs so they use less power
- Restructuring logic to reduce dynamic power
- Correctly selecting logic inputs to minimize capacitance on high-toggling nets
- Reducing area and wiring demand for core logic to minimize dynamic power in routing
- Modifying placement to reduce clocking power
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