MAX 7000 CPLD Family Features

Altera's MAX^® 7000 CPLDs contain system-level features that offer exceptional performance and that earned them, along with other Altera^® MAX devices, leadership among CPLDs. Follow the links in Table 1 to find out more about the system features of MAX 7000 devices.

Notes:

1. PLCC = plastic J-lead chip carrier
2. TQFP = thin quad flat pack
3. PQFP = plastic quad flat pack
4. BGA = ball-grid array
5. RQFP = power quad flat pack

Device Programming

MAX 7000 devices support ISP and Joint Electron Device Engineering Council (JEDEC)-approved Jam STAPL through the built-in IEEE 1149.1 JTAG interface. ISP enables in-field upgrades and reduces the need for expensive hardware reworking. Jam STAPL complements ISP by providing a software-level standard for in-system programming. MAX 7000 devices provide a built-in JTAG boundary-scan test circuitry, and can be programmed using in-circuit testers, embedded processors, and programming hardware from Altera or third-party vendors. Table 2 shows the device programming options for MAX 7000 devices.

Table 2. Device Programming Options for MAX 7000 Devices
Mount Unprogrammed	Program In-System	Reprogram in the Field
No device handling No bent leads	Allows generic inventory Easy prototyping Supports changes during manufacturing and test flow	Allows field upgrades Add enhancements quickly and easily

For information on Altera ISP support, go to the Altera Support for In-System Programmability page.

Both MAX 7000AE and MAX 7000B devices are compliant to the IEEE 1532 hardware standard. IEEE 1532 enables concurrent in-system programming of multiple devices in minimum time, and addresses both silicon and software issues to create a homogeneous ISP environment.

Hot-Socketing

MAX 7000AE and MAX 7000B devices can tolerate any possible power-up sequence. The V_CCIO and V_CCINT power planes can be powered in any order. Signals can be driven into MAX 7000AE and MAX 7000B devices before and during power up without damaging the devices.

For detailed information on the hot socketing feature, go to the On-Chip Hot Socketing & Power Sequencing Support in Altera Devices page.

Programmable Power-Saving Mode

MAX 7000 devices offer a programmable power-saving mode that provides programmable speed and power optimization. Most logic applications require only a small fraction of all gates to operate at maximum frequency. Designers using MAX 7000 devices can configure one or more macrocells to operate at 50 percent or lower power, while adding only a nominal timing delay. With this power-saving feature, only the speed-critical portions of a design run at high speed or full power, while the remaining portions run at reduced speed or low power.

PCI Compatibility

PCI local bus standards serve the standard interface in embedded systems, as well as in desktop computers. PCI-compatible devices are found in many applications, such as network adapters, system area networks, embedded controllers, graphic accelerator boards, and servers. Altera's MAX 7000B, MAX 7000AE, and MAX 7000S devices are PCI-compatible and can integrate these high-performance PCI applications. Refer to the MAX 7000 device family data sheets for specific information on PCI compatibility.

Operating Temperatures

Because Altera CPLDs support a wide range of operating temperatures, they are ideal for many applications. All MAX 7000 CPLDs are available in the commercial temperature range of 0°C to +70°C (ambient) and the industrial temperature range of -40°C to +85°C (ambient). The MAX 7000AE family is also qualified to an extended temperature range of -40°C to +130°C (junction) and offered in automotive-grade devices.