MAX 7000 CPLD Family Overview

Altera's MAX^® 7000 CPLD family provides a high-performance programmable logic solution with densities ranging from 600 to 10,000 usable gates (32 to 512 macrocells). With predictable performance, instant-on capability and breadth of packaging options, MAX 7000 is the most comprehensive programmable logic solution in its density class.

Tables 1 to 3 list the offerings of the MAX 7000B, MAX 7000AE, and MAX 7000S devices.

Notes:

1. t_PD (ns) = Data path delay from input to non-registered output
2. t_SU (ns) = Global clock setup time
3. t_FSU (ns) = Global clock setup time of fast input
4. t_CO1 (ns) = Delay from global clock to output
5. f_CNT (ns) = 16-bit counter internal global clock frequency
6. PLCC = Plastic J-lead chip carrier
7. TQFP = Thin plastic quad flat pack
8. Ultra FineLine BGA = 0.8-mm pitch ball-grid array
9. FineLine BGA = 1.0-mm pitch ball-grid array
10. PQFP = Plastic quad flat pack
11. BGA = Ball-grid array
12. RQFP = Power quad flat pack

To sample or to purchase MAX 7000 devices, contact your nearest Altera^® sales representative or distributor.