The MercuryTM architecture is built for bandwidth. It offers a high-speed core that processes data at gigabit data rates and manages the clock data recovery (CDR)-generated bandwidth of 45 Gbps. The combination of high-performance features such as a high-speed prioritized interconnect, quad-port RAM capability, and distributed multiplier circuitry facilitates a high data throughput, providing an optimal solution for complex design requirements. Figure 1 shows the features of the Mercury device architecture.
Figure 1. The Mercury Architecture
Prioritized Interconnect Structure
The Mercury architecture features a prioritized interconnect structure that intelligently prioritizes signal routing to maximize performance. The prioritized interconnect structure consists of four elements (see Figure 2):
- Priority row and column lines have wider signal traces and larger line drivers, allowing for the fastest possible routing times for speed-critical signals.
- Dedicated leap lines accelerate row-to-row connections. These structures make direct connections to adjacent row lines possible and speed communication across rows, removing traditional limitations and increasing system speed.
- RapidLABTM interconnect provides fast connections to neighboring logic array blocks (LABs). These direct connections within a span of any ten LABs reduce the distance signals need to travel and minimize propagation delay.
- FastLUTTM interconnect provides the fastest possible direct connection between adjacent logic elements (LEs) and enables seamless implementations of wide fan-in functions.
Figure 2. Mercury Prioritized Interconnect Structure
