Altera's Mercury™ device family offers programmable application-specific standard product (ASSP) functionality with advanced clock data recovery (CDR) technology. Mercury CDR is capable of speeds at up to 1.25 Gbps per channel and a total CDR bandwidth of 45 Gbps, and is made possible by dedicated HSDI circuitry, shown in Figure 1. Mercury devices introduce programmable logic devices (PLDs) to a variety of applications that could previously be implemented only in ASSPs.
Figure 1. Mercury CDR Interface
CDR is a key element in today's leading-edge communications systems, empowering applications in high-speed backplane, chip-to-chip, and line-side systems. Figure 2 shows CDR functionality, with a CDR transmitter embedding the clock in the data stream on one end, and a CDR receiver recovering the clock from the data on the other end. This functionality allows for higher transmission speeds, ensures that the data and clock are always perfectly in phase, and relieves board trace routing restrictions.
Figure 2. Transmitting & Receiving with CDR
Dedicated CDR circuitry enables Mercury devices to eliminate frequency barriers faced by source-synchronous systems. Today's high-performance communications systems often require data transmission at speeds in excess of 1 Gbps. Typically, single-ended I/O standards reach noise limitations at frequencies of about 250 MHz before signal integrity deteriorates. Differential I/O standards solve this problem with common mode rejection, allowing data transmission with fewer pins at higher speeds. However, clock skew becomes an issue for differential I/O standards when the frequency nears 1 Gbps. CDR is the necessary technology to eliminate such barriers, and enables data transfer at speeds beyond these limits. Figure 3 illustrates the need for CDR at speeds of 1 Gbps and beyond.
Figure 3. Clock Management with CDR
CDR removes clock skew concerns by encoding the clock into every data stream, guaranteeing that the clock and data are always perfectly in phase. This capability eliminates tight routing signal requirements, removing the need for a specified relationship between clock and data lines, as shown in Figure 4. CDR also eliminates topology restrictions, allowing designers to create systems with many independent clock domains and multi-crystal operation.
Figure 4. CDR Benefits
CDR Applications
CDR is required for many of today's high-performance applications. For example, a system backplane such as the one in Figure 5 is a critical component of the overall performance of systems such as network routers or switches. Implementation of these high-speed serial backplanes demands a fast data transfer rate, support for independent clocks, and programmable logic for the designer to complete the system design. Mercury devices offer these essential features and provide the optimal solution for high-speed backplanes.
Figure 5. System Backplane
High-speed serial connections are used between system components in network topologies. From the physical interface (PHY) layer, to the network processor, to the traffic manager, to the fabric system, using high-speed serial connections can significantly enhance design performance and flexibility. In these systems, the PHY layer handles communication with the outside world, and therefore must comply with communication standards such as Gigabit Ethernet or SONET/SDH. Meanwhile, the ability to implement proprietary logic between layers allows maximum system performance. Mercury devices are ideal for both of these situations, as they support a variety of today's leading edge standards (shown in Table 1) while providing top-tier programmable logic to implement value-added designs.
| Table 1. CDR & LVDS Applications | |||
|
Application
|
Bandwidth
(Mbps)
|
Channels
|
Mercury
|
|
SONET/SDH Standards
|
9,953
|
8
|
|
|
POS-PHY L4
|
9,953
|
8
|
|
|
RapidIO
|
8,000
|
16
|
|
|
Gigabit Ethernet
|
1,250
|
Any
|
|
|
HDTV
|
742.6
|
Any
|
|
|
Proprietary Backplanes
|
Any
|
Any
|
|
The Mercury CDR Solution
Mercury devices offer 8 to 18 CDR channels per device, with each channel capable of speeds up to 1.25 Gbps. By integrating the CDR function with programmable logic in Mercury devices, Altera allows system designers to save valuable board space and costs. Figure 6 illustrates CDR ASSP functionality.
Figure 6. Programmable ASSP
Mercury devices support data speeds from 125 Mbps to 1.25 Gbps. As the requirement for more I/O bandwidth and system complexity increases, devices with CDR capability become a key component in the development of next-generation systems. The Altera® Mercury device family provides the CDR function as a key part of the programmable ASSP solution.
Related Links
AN 130 (CDR in Mercury Devices, version 1.0, February 2001) (226Kb)
Mercury High-Performance I/O Capabilities
Mercury Performance-Optimized Architecture
