On 22 open core designs (obtained from www.opencores.org) the latest benchmarking comparison of Stratix® II and Virtex-5 FPGAs show that Stratix II devices, because of their highly efficient 8-input fracturable LUT logic architecture, are 18% faster than currently available Virtex-5 devices. All speed grades in the Stratix II family have been shipping since July 2004.
Table 1 lists the Stratix II and Virtex-5 FPGAs compared in this recent benchmark.
| Table 1. Stratix II and Virtex-5 FPGAs | |||
| Device |
Speed Grade |
Description |
Available |
| Stratix II (-3) |
-3 |
Fast |
Yes |
| Virtex-5 (-1) |
-1 |
Slow |
Yes |
| Virtex-5 (-2) |
-2 |
Medium |
No |
Figure 1 compares Stratix II (-3) to available Virtex-5 (-1) devices, highlighting the Stratix II FPGA's significant performance advantage of 18%.
Figure 1. Stratix II (-3) vs. Virtex-5 (-1) FPGA Performance Comparison
Figure 2 compares Stratix II (-3) to Virtex-5 (-2) devices. Virtex-5 (-2) (i.e., medium speed grade) is currently not available, and benchmarking results show that Virtex-5 (-2) is at par with Stratix II (-3) performance.
Figure 2. Stratix II (-3) vs. Virtex-5 (-2) FPGA Performance Comparison
Open Core Benchmark Details
The open core designs were selected based on their popularity, and they are all written in generic hardware description languages (HDLs). To provide a fair comparison, no manual optimization of the design code was done, except for getting the designs to compile and making the RAM modules to target both FPGA architectures.
Run Your Own Performance Benchmark
It's easy to run your own performance comparisons by using the publicly available open core designs. For Stratix II FPGAs, use the Quartus® II performance optimization settings shown in Table 2. Make sure to set timing constraints for each clock. For open core performance benchmarks, each clock is set to 1 GHz (in normal practice you should set the clock constraints to your actual needs for best results).
More details on benchmark settings and performance optimizations are available in the Three Steps to Higher Performance page and details on benchmarking methodology at Altera are available on the benchmarking methodology page.
|
Table 2. Quartus II Performance Optimization Options |
|
|
Options |
Setting |
|
Analysis & Synthesis Settings—Optimization Technique |
Speed |
|
Design Space Explore Advanced Search—Exploration Space |
Physical Synthesis |
|
Design Space Explore Advanced Search—Optimization Goal |
Optimize for Speed |
|
Design Space Explore Advanced Search—Search Method |
Accelerated Search of Exploration Space |
| Table 3. Learn More about Stratix II FPGAs | |
| Feature |
Description |
| Performance Comparison | Compare Stratix II Performance with Competing Devices |
| Technical Papers | The Stratix II Logic and Routing Architecture Technical Paper |
| Improving FPGA Performance and Area Using an Adaptive Logic Module | |
| Fracturable FPGA Logic Elements | |
| Architecture | FPGA Architecture White Paper |
| Performance and Logic Efficiency Analysis White Paper | |
| 8-Input Fracturable LUT in the ALM | |
| Design Building Blocks | |
| Embedded Adders | |
| DSP | DSP Blocks |
| DSP Performance Center | |
