Step 1: Defining Stratix II Logic Structure

This page is the first of three pages that describe the high-performance Stratix^® II FPGA development process:

• Step 1: Defining Stratix II Logic Structure
• Step 2: Designing Stratix II Adaptive Logic Module
• Step 3: Delivering tomorrow's performance today with Stratix II FPGAs

In 2002, Altera needed a new solution to address the challenges of 90-nm FPGA technology and meet customers' requirements:

• Increased performance
• Reduced power consumption
• Increased logic density
• Seamless integration of architecture into software

Figure 1 illustrates the trade-off between relative cost and delay for different LUT sizes. Research (PDF) had shown that wider look-up tables (LUTs) provide better performance, while FPGA logic fabric with a narrower LUT is more cost-effective. Hence there was room for improvement in the FPGA, and the results challenged the traditional 4-input LUT logic structure.

Figure 1. Conceptual View of Relative Performance, Cost-Effectiveness, and LUT Input Size Comparison

Multiple input LUT configurations are required in every design, as evidenced by a study on a suite of customer designs. The LUT distribution is shown in Figure 2.

Figure 2. LUT Distribution from Synthesis

An exhaustive iterative process was then conducted, in which over 150,000 experiments were run by the engineering team at Altera to optimize the new logic structure of Stratix II FPGAs for efficiency.

A delicate balance between cost and performance gave birth to the concept of fracturability of the LUT structure in Stratix II FPGAs.

Figure 3 shows that starting from synthesis to placement and routing in the Quartus^® II software, a flexible 8-input fracturable LUT was required to accommodate the various distribution of LUT configurations to maximize performance. The fracturability avoids wasting logic because of unused resources when the LUT is configured with smaller functions.

Figure 3. LUT Innovation Methodology

The MultiTrack Interconnect

In addition to the innovative 8-input fracturable LUT, the Stratix FPGA series introduced the MultiTrack interconnect to maximize connectivity and performance. It provides the industry's best connectivity with up to five times the logic in a single hop compared to the competition. The Stratix FPGA series connectivity is shown in Figure 4.

Figure 4. Stratix FPGA Series MultiTrack Interconnect Connectivity

Advantages of the MultiTrack interconnect:

• Provides more accessibility to any surrounding LAB with much less connections, thus improving performance and reducing power
• Avoids area congestion to provide better logic packing

Figure 5. The 8-Input Fracturable LUT in the ALM

The ALM is capable of implementing all 6-input functions, select 7-input functions or can fractured into smaller LUTs to implement 2 independent functions.

Advantages of Stratix II ALM:

• Produces shorter combinatorial logic levels to achieve 50% faster performance compared to the previous-generation FPGA
• Effectively packs more logic in any single FPGA and contains 80% more logic than the nearest competing logic cell.
• Has full integration with the Quartus II software to optimally utilize the 8-input fracturable LUT in the ALM and the routing interconnect architecture of Stratix II FPGAs.