Step 2: Designing Stratix II Adaptive Logic Module (ALM)

This page is the second of three pages that describe the high-performance Stratix^® II FPGA development process:

• Step 1: Defining the Stratix II Logic Structure
• Step 2: Designing the Stratix II Adaptive Logic Module (ALM)
• Step 3: Delivering tomorrow's performance today with Stratix II FPGAs

Defining the logic structure was a crucial step in the designing of Stratix II FPGAs. However, additional features were designed into the ALMs—the basic building block of Stratix II devices—that maximized efficiency and performance. The available resources in the ALM are shown in Figure 1 and are listed in Table 1.

Figure 1. Stratix II ALM

The ability to expand and share the LUT inputs allows each Stratix II ALM to absorb more logic capacity than traditional 4-input LUT structures for an equivalent function. The larger logic capacity in Stratix II ALMs not only reduces the total logic utilization but also reduces the average routing utilization (shown in Figure 2) improving the overall performance of your design.

Figure 2. Stratix II Devices Reduce Average Routing Utilization

Stratix II Logic Structure Benefits

• Produces shorter combinatorial logic levels to achieve 50% faster performance compared to previous generation FPGA.
• Is fully integrated with Quartus II software to optimally utilize the 8-input fracturable LUT in the ALM and the routing interconnect architecture of Stratix II FPGAs.
• More efficient and very little logic wasted compared to the nearest competing logic cell.