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Stratix II vs. Virtex-4 Open Core Performance Benchmark

Home > Products > Devices > Stratix II vs. Virtex-4 Open Core Performance Benchmark

Related Links

  • FPGA Architecture White Paper
  • Stratix II vs. Virtex-5 FPGA Open Core Benchmark
  • Compare Stratix II FPGA Performance with Competing Devices

Compare Stratix II Performance with Competing Devices

See Stratix II Performance Advantage

Altera tested 25 open core designs (obtained from www.opencores.org) to benchmark Stratix®  II and Virtex-4 FPGA performance. Results showed that Stratix II FPGAs are a full speed grade faster than Virtex-4, proving Stratix II devices to be the fastest FPGAs in the 90-nm process node.

Open Core Benchmark Details

The 25 open core designs were selected based on their popularity, and they are all written in generic hardware description languages (HDLs). Designs were synthesized using Synplify Pro software version 8.0 and compiled using Quartus® II software version 5.0 or ISE software version 7.1i service pack 1. Similar to the customer design benchmark, the open core designs use the fastest speed grade devices available in each software and are compiled for maximum performance.

To provide a fair comparison, no manual optimization of the design code was done, except for getting the designs to compile and making the RAM modules to target both FPGA architectures. Figure 1 shows the results of the open core performance benchmark.

Figure 1. Stratix II vs. Virtex-4 FPGA Open Core Performance Benchmark

Figure 1. Stratix II vs. Virtex-4 Open Core Performance Benchmark

The open core performance benchmark results shows that, on average, Stratix II FPGAs are one speed grade faster than Virtex-4 devices. This is the same as the result obtained through the customer design benchmark.

Run Your Own Performance Benchmark

It's easy to run your own performance comparisons by using the publicly available open core designs.

For Stratix II FPGAs, use the Quartus II performance optimization settings shown in Table 1. Make sure to set timing constraints for each clock. For open core performance benchmarks, each clock is set to 1 GHz (in normal practice you should set the clock constraints to your actual needs for best results).

More details on benchmark settings and performance optimizations are available in the Three Steps to Higher Performance page.

Table 1. Quartus II Performance Optimization Options

Options

Setting

Analysis & Synthesis Settings—Optimization Technique

Speed

Design Space Explore Advanced Search—Exploration Space

Physical Synthesis

Design Space Explore Advanced Search—Optimization Goal

Optimize for Speed

Design Space Explore Advanced Search—Search Method

Accelerated Search of Exploration Space

Table 2. Learn More about Stratix II FPGAs 
Topic

Description

Performance Comparison Compare Stratix II Performance with Competing Devices
Logic FPGA Architecture White Paper
8-Input Fracturable LUT in the ALM
Design Building Blocks
Embedded Adders
Achieving More Performance 3 Steps to Higher Performance
DSP DSP Blocks
DSP Performance Center
Benchmarking Benchmarking Methodology White Paper
Benchmarking Methodology

Developing Stratix II FPGAs

  • Step 1: Defining Stratix II Logic Structure
  • Step 2: Designing Stratix II Adaptive Logic Module
  • Step 3: Delivering Stratix II with High Performance
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