Stratix II vs. Virtex-5 Logic Efficiency
- The Stratix II FPGA's adaptive logic module (ALM) is efficient compared to the LUT-FF pair of Virtex-5, thus enabling Stratix II FPGAs to deliver tomorrow's performance today
- Benchmarking results on 65 customer designs show that, on average, the Stratix II ALM "is equivalent to" or "can hold as much logic as" 1.8x Virtex-5 logic elements (LEs).
Figure 1 shows the ratio of Virtex-5 LUT-FF pairs to Stratix II FPGA's ALM on a set of 65 customer designs. The horizontal black line at the "1" mark indicates a point at which the number of LEs for Virtex-5 (LUT_FF pair) and Stratix II FPGAs (ALM) are the same. On average, the Stratix II FPGA's ALM has a 1.8x advantage over Virtex-5 and can go as high as 2.3x on certain designs.
Figure 1. Logic Efficiency Comparison
The ALM has 8 inputs with the capability of implementing a full 6-LUT, select 7-input functions, and can also be efficiently fractured into independent smaller LUTs. This makes the ALM of Stratix II devices highly efficient as compared to the Virtex-5 LE. Figure 2 shows the Stratix II FPGA's ALM and the Virtex-5 LUT-FF pair, and Table 1 highlights their respective LEs.
Figure 2. Stratix II ALM
The Virtex-5 logic element (LUT-FF Pair) consists of a basic 6-input LUT (inflexible LUT structure), carry logic and a single register as shown in Figure 3. The 6-input LUT has the ability to implement smaller size functions but it results in unused configuration bits, wasted silicon area and higher cost.
Figure 3. Virtex-5 LUT-FlipFlop Pair
| Table 1. Stratix II ALM and Virtex-5 LUT-FF Pair Feature Comparison |
|
Feature
|
ALM
|
LUT-FF Pair
|
|
Number of Inputs
|
8
|
6
|
|
Number of Outputs
|
2
|
2
|
|
Fracturable LUT
|
Yes
|
No
|
|
Register Count per LUT
|
2
|
1
|
|
Dedicated Full Adders
|
2
|
0
|
Table 2 below shows just a few combinations of function and compares the number of inputs shared for Stratix II and Virtex-5.
|
Table 2. Stratix II ALM vs. Virtex-5 LUT Flexibility
|
|
Output 1
|
Output 2
|
# of Shared Inputs (Minimum) for Virtex-5 LUT
|
# of Shared Inputs (Minimum) for Stratix II ALM
|
|
5-LUT
|
5-LUT
|
5
|
2
|
|
5-LUT
|
4-LUT
|
4
|
1
|
|
5-LUT
|
3-LUT
|
3
|
0
|
|
4-LUT
|
4-LUT
|
3
|
0
|
|
4-LUT
|
3-LUT
|
2
|
0
|
|
3-LUT
|
3-LUT
|
1
|
0
|
Developing Stratix II FPGAs
|
Literature
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