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High-Performance FPGA Architecture

Home > Products > Devices > About Stratix Series > High-Performance FPGA Architecture

With the introduction of the Stratix® II FPGA family came the first revolution in high-performance FPGA architectures in several years—the adaptive logic module (ALM). Since then, all high-density Stratix series FPGA families have utilized the ALM structure and all of the benefits it brings. The Alms are routed with the MultiTrack interconnect architecture, enabling a Stratix series FPGA to implement high-speed logic, arithmetic, and register functions. The Alms are fully integrated in Quartus® II development software to easily deliver the highest performance, highest logic utilization, and lowest compile times.

For more details on the Stratix and Stratix GX FPGA architectures see the respective handbook chapters.

The key to high performance in a Stratix series FPGA is the area-efficient ALM. It has 8 inputs with a fracturable look-up table (LUT) that can be divided into two adaptive LUTs (ALUTs) using Altera's patented LUT technology. Each ALM is capable of implementing:

  • A full 6-input LUT or select 7-input LUT
  • Two independent outputs of multiple combinations of smaller LUT sizes for efficient logic packing
  • Complex logic-arithmetic functions without additional resources

Figure 1 and Table 1 outline the structure and features of valid configurations available within the ALM.

Figure 1. ALM Structure

Table 1. ALM Features and Advantages

Available Resources per ALM

Advantages

8-Input Fracturable LUT
  • Can implement any 6-input logic function and certain 7-input functions and be fractured into independent smaller LUTs, such as two independent 4-input LUTs
  • Quartus II software design suite integrates this fracturability and optimizes it for performance, efficiency, power, and area (more logic capacity and less wasted logic)
Two Embedded Adders
  • Allows for two two-bit additions or two three-bit additions without any additional resources
  • Operands can be generated from the same ALM and do not require any additional logic
Two Registers
  • Optimal register-to-logic ratio to ensure device is not register-limited
  • Abundance in registers for register-rich applications or pipeline designs for performance
Two Outputs
  • Inputs of a single ALM can be divided between the two output functions, allowing wide input functions to run fast and narrow input functions to efficiently use remaining resources
MLAB
  • The core of a Stratix series FPGA is a second variation of the logic array block (LAB), known as the MLAB, that can be used as a regular ALM or configured as simple dual-port SRAM blocks
  • Part of the TriMatrix memory technology, MLABs can be configured as 64 x 10 or 32 x 20 simple dual-port SRAM blocks. The MLABs are optimized to implement filter delay lines, small FIFO buffers, and shift registers with maximum performance of 600-MHz clock speeds

Refer to the Logic Array Blocks and Adaptive Logic Modules (PDF) chapter of the Stratix IV Device Handbook for more information.

The MultiTrack Interconnect

High-performance Stratix series FPGAs leverage the MultiTrack interconnect technology. This technology consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks.

The MultiTrack interconnect technology, shown in Figure 2, is used in Altera's Stratix FPGA series to:

  • Provide the industry's best connectivity with up to five times the logic in a single hop (compared to the competition)
  • Provide more accessibility to any surrounding LAB with much fewer connections, thus improving performance and reducing power
  • Avoid area congestion to provide better logic packing

Figure 2. Stratix FPGA Series MultiTrack Interconnect Connectivity

Advantages of Altera's High-Performance FPGA Architecture

The fracturable LUT, two full adders, two registers, and additional logic enhancements that enable the ALM to be partitioned into two independent LUTs for maximum efficiency make Stratix series FPGAs the fastest and biggest FPGAs in their respective class—with no wasted logic.

Related Links

  • Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices (PDF)
  • Logic Array Blocks & Adaptive Logic Modules in Stratix III Devices (PDF)
  • Stratix II Architecture (PDF)
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