Based on the wildly successful first generation Nios® embedded processor, the Nios II family of embedded processors delivers three processor cores to address an even wider range of embedded processing applications. You can choose from a high-performance core (over 200 DMIPS), a low-cost core (as low as 35 cents in logic) and a performance-/cost-balanced standard core. The Nios II family of processors addresses tasks such as:
- Implementing complex state machines
- Off-loading existing processors
- Performing I/O and data-processing tasks
- Configuring FPGAs remotely
- Accelerating digital signal processing (DSP) algorithms
The advanced architectural features of high-performance Stratix® series FPGAs, combined with Nios II embedded processors, offer unparalleled processing power to meet the needs of high-bandwidth systems. With Nios II processor-based systems (including a processor core and peripherals) starting at around 2,000 equivalent logic elements (LEs), Stratix series FPGAs can easily fit complete system functions into a single device, satisfying the needs of networking, telecommunications, digital signal processor, and mass storage applications.
Stratix Series FPGA Architecture
The architecture of an FPGA in the Stratix series provides further technology enhancements that benefit complex intellectual property (IP) blocks, such as the Nios II embedded processor, both in terms of higher fMAX and lower resource utilization.
The logic structure in Stratix series FPGAs has been enhanced to allow it to perform certain frequently used functions efficiently. This works well with system blocks such as the Avalon® system interconnect fabric. The wide input function support found in Stratix series FPGAs means that as the system increases in complexity, the performance penalty is reduced.
Nios II processors include several CPU-optimization options, allowing them to benefit from the ability of Stratix series FPGAs to implement a single cycle-multiply function in a single DSP block. This implementation can save 370 LEs and hundreds of clock cycles when compared to a soft implementation. In the same way, the Stratix series FPGA adaptive logic modules (ALMs) ternary adder support further reduces the size of the Nios II processor's arithmetic logic unit (ALU).
The embedded DSP blocks in the Stratix series FPGA architecture also provide the perfect complement to Nios II custom instructions and other hardware acceleration units. DSP designers can now create DSP algorithms and complex math routines in high-performance hardware DSP blocks and access them as regular software routines or implement them as custom instructions to the Nios CPU. For example, in a voice-over-IP (VOIP) application, an echo-cancellation algorithm can be implemented in hardware and directly executed in software using a custom instruction. This gives DSP designers the flexibility and portability of high-level software design while maintaining the performance benefits of parallel hardware operations in FPGAs—without resorting to excessive clock speeds.
The TriMatrix memory in Stratix Series FPGAs caters to all the memory needs of a typical system-on-a-chip (SOC) solution. This memory architecture has been modified to meet both customer needs and Nios II usage models in each Stratix series FPGA family. The abundant TriMatrix memory blocks can implement on-chip cache memory for accelerating off-chip memory access and significantly increasing overall software performance in embedded systems, while the large blocks are suited for mass code storage for the Nios II processor.
Stratix Series FPGAs and Nios II Processors: A Complete System Solution
The Stratix Series FPGA architecture is ideal for the block-based design methodology that is required for designing large systems using pre-optimized IP modules or re-using existing design modules.
Altera's SOPC Builder automated system development tool provides you with a powerful platform for composing bus-based systems out of common system components such as processors, peripherals, and memory interfaces. SOPC Builder-generated systems are pre-optimized IP blocks that benefit significantly from the Stratix II architecture.
The Nios II peripherals and interfaces library web page has more details on the peripherals available for the Nios II processors.
