Leading-edge ASIC designs are becoming a more expensive and time-consuming operation because of the increasing cost of mask-sets and the amount of engineering verification required. Getting a device right the first time is imperative. A single missed deadline can mean the difference between profitability and failure in the life cycle of a product. Figure 1 shows how the sales of a product can be affected due to time-to-market delays.
Figure 1. Declining Product Sales Due to Late-to-Market Designs
Using an FPGA to prototype an ASIC or ASSP for verification of both register transfer level (RTL) and initial software development has now become standard practice to both decrease development time and reduce the risk of first silicon failure. An FPGA prototype accelerates verification by allowing testing of a design on silicon from day one, months in advance of final silicon becoming available. Code can be compiled for the FPGA, downloaded, and debugged in hardware during both the design and verification phases using a variety of techniques and readily available solutions. Whether you're doing RTL validation, initial software development, and/or system level testing, FPGA prototyping platforms deliver a higher degree of confidence in your ability to deliver an end working product. For more on this topic, view the related links listed below.
Altera's Stratix® III and Stratix IV family of FPGAs are ideal for ASIC prototyping, offering the highest density of any 65-nm FPGA available today. Designs of up to 8+ million ASIC gates (i.e., 2-input NAND gates) plus 23 Mbits of memory and 1,360 digital signal processing (DSP) blocks available as additional resources can be implemented in a single Stratix III EP3SL340 device. Details of the larger devices in the Stratix III and Stratix IV FPGA families are shown in Table 1.
| Table 1. Largest Devices of Stratix III and Stratix IV FPGA Families | |||||||
| Device | Logic Elements (LEs) | ASIC Gates | User I/Os | Total Memory Bits |
18 x 18 Multipliers |
Phase-Locked Loops (PLLs) | |
|---|---|---|---|---|---|---|---|
| EP3SL200 | 198,900 | 2.4M | 976 | 7.7M | 576 | 12 | |
| EP3SE260 | 254,400 | 3.1M | 976 | 14.6M | 768 | 12 | |
| EP3SL340 |
338,000 |
4.1M |
1,120 |
16.3M |
576 |
12 |
|
| EP4SE360 |
353,600 |
4.2M |
744 |
18.1M |
1,040 |
16 |
|
| EP4SE530 |
531,200 |
6.4M |
976 |
20.7M |
1,024 |
16 |
|
| EP4SE820 | 820,000 |
15M |
1,120 |
23.1M |
960 |
16 |
|
Double Platform Logic Capacity—Upgrade from a Stratix III to a Stratix IV FPGA
Altera recognizes that the up-front NRE for development of an ASIC prototyping platform is not a trivial amount of engineering time and cost. When designing the next generation 40-nm Stratix IV devices, Altera recognized that it was important for customers to easily migrate from the largest Stratix III devices to the largest Stratix IV devices to preserve existing platform development efforts, thereby reducing both follow-on development time and cost. For more information about the upgrade path, see the Stratix IV FPGA Family Overview page.
For larger ASIC designs that don't fit into a single FPGA, using multiple FPGAs for prototyping becomes a matter of partitioning a design across FPGAs and ensuring design interconnects (e.g., bus signals) are maintained. Using the biggest FPGA available reduces the number of FPGAs required to implement a prototype, thereby reducing the number of interconnects required between devices. For any interconnect scheme, Stratix III and Stratix IV FPGAs offer the highest performance with best-in-class signal integrity I/O pins, whether using LVDS or SSTL, allowing the FPGA prototype to perform as close to the initial design goals of the ASIC as possible.
Our largest Stratix III FPGAs are fully supported by major ASIC EDA vendors for software solutions, as well as third-party board vendors for off-the-shelf multi-FPGA solutions. Altera's Quartus® II design software integrates into design flows that are close to, if not identical to, a typical ASIC flow reducing the amount of learning required when using a new software tool. In addition, the tools can be invoked using scripting to match commonly used ASIC design methodologies.
Our largest Stratix III FPGAs also offer the industry's only low-risk development path from FPGA prototype to high-volume ASIC production with support for migration to HardCopy® ASICs. Designing for a HardCopy III ASIC allows you to reduce development costs and still get the flexibility and time-to-market advantages associated with an FPGA.
All of the Altera intellectual property (IP) cores that support Stratix III FPGAs can be licensed for use in an ASIC. The advantage of an Altera IP core is that the IP is optimized to the Stratix III family architecture, allowing it to run at ASIC-like speeds.
ASIC Prototyping EDA Partners
To aid and support the development of high-density designs, Altera has developed an ecosystem of EDA software partners and development board partners that help facilitate the complete design process.
ASIC Prototyping Third-Party Board Partners
The following lists the third-party board partners that provide off-the-shelf ASIC prototyping and verification solutions utilizing Altera® FPGAs:
