With up to 12 phase-locked loops (PLLs) and a hierarchical clocking scheme providing up to 48 unique clock domains per device, Altera® Stratix™ devices are built to function as the central clock manager to meet your system timing challenges. These devices are the first FPGAs to offer on-chip PLL features previously found only in high-end discrete PLL devices features such as spread-spectrum clocking, clock switchover, frequency synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth. Stratix devices also offer PLL reconfiguration, allowing users to change the PLL configuration without reprogramming the entire device. Stratix PLLs increase system and device performance and provide advanced clock interfacing and clock-frequency synthesis.
Figure 1 shows a block diagram of the Stratix PLL.
Figure 1. Stratix PLL Block Diagram
Altera Stratix devices have two types of PLLs: enhanced PLLs and fast PLLs. Enhanced PLLs are feature-rich general-purpose PLLs supporting advanced features such as external feedback, clock switchover, PLL reconfiguration, spread-spectrum clocking, and programmable bandwidth. Fast PLLs are optimized for high-speed differential I/O interfaces and can be used for general-purpose, PLL clocking. Table 1 outlines the enhanced and fast PLL features found in Stratix devices.
| Table 1. Stratix PLL Features | ||
| Features |
Enhanced PLL
|
Fast PLL
|
| Input Frequency Range |
3 - 462 MHz
|
30 - 644.5 MHz
|
| Output Frequency Range |
0.6 - 462 MHz
|
9 - 644.5 MHz
|
| Programmable Phase Shift |
160 ps
|
160 ps
|
| Programmable Delay Shift | 250-ps increments(1) | |
| Clock Switchover |  |
|
| PLL Reconfiguration | |
|
| Programmable Bandwidth | |
|
| Spread-Spectrum Clocking | |
|
| Number of Dedicated External Differential Clock Outputs | 8 (2) | (3) |
| Number of Feedback Clock Inputs | 4 (4) | |
| Number of PLLs per Device | Up to 4 | Up to 8 |
- 250-ps increments for a range of -3.0 ns to +3.0 ns between any two outputs.
- Every Stratix device has two enhanced PLLs with eight external single-ended or four external differential outputs. Two additional enhanced PLLs in EP1S40, EP1S60, EP1S80, and EP1S120 devices each have one single-ended external output.
- Every Stratix device has two enhanced PLLs with one external single-ended or external differential feedback input per PLL.
- Fast PLLs drive out differential clocks via the high-speed differential I/O pins.
System-Level Clock Management
Each Stratix device has two PLLs with dedicated outputs to manage board level system timing. There are up to a total of 16 single-ended or eight differential outputs. These outputs can be used to provide clocks to other devices in the system, eliminating the need for other clock sources on the board. Users can utilize a combination of the features provided in the Stratix PLLs, such as programmable phase shift, external feedback, and delay to compensate for board-level skew and delays.
Clock Network
Each Stratix device has up to 16 high-performance, low-skew global clocks that can be used for clocking high-performance functions or global control lines. Additionally, six localized (regional) clocks per region increase the total number of clocks for any region to 22. This web of high-speed clock lines, which are tightly coupled with the abundant PLLs, ensures that the most complex design can run at optimal performance and with minimum clocking skew.
