Stratix II GX High-Performance Architecture
The Stratix® II GX device architecture has two distinctly different functional regions that seamlessly work together: gigabit transceiver blocks and a general-purpose logic structure, which includes adaptive logic modules (ALMs), digital signal processing (DSP) blocks, TriMatrix memory blocks, and phase-locked loops (PLLs). Additionally, Stratix II GX devices provide varieties of I/O pins, including standards in source-synchronous signaling I/O, differential I/O, and single-ended I/O categories.
Figure 1. Stratix II GX EP2SGX60E Floorplan
6.375-Gbps Transceiver Technology
The high-performance, programmable Stratix II GX architecture contains up to 20 independent, full-duplex channels that support serial bit rates across the entire operating range of 600 Mbps to 6.375 Gbps with excellent performance. The transceivers support PCI Express, 10 Gigabit Ethernet XAUI, Gigabit Ethernet, SDI, SONET, Serial RapidIOTM, SerialLite II, and proprietary protocols.
Each transceiver has circuitry that ensures smooth, seamless data transfer from the block to the rest of the device for processing and manipulation. This circuitry prevents data bottlenecks that can degrade performance and reduce data bandwidth. The logic array and transceivers can exchange data as an 8-, 10-, 16-, 20-, 32-, or 40-bit bus.
Each transceiver has serializer/deserializer (SERDES) and multiplexing/de-multiplexing circuitry that translates the high-speed serial input stream to a width and frequency suitable for processing within the logic array. Additionally, each transceiver has PLLs that multiply or divide the incoming reference clock to serialize or deserialize the outgoing or incoming data.
Maximized Interconnect Performance
Like Stratix II devices, Stratix II GX devices have a MultiTrack interconnect with DirectDrive technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks. DirectDrive technology is a proprietary, deterministic routing technology that ensures identical routing resource usage for any function, regardless of its placement within the device. This technology greatly simplifies the system integration stage of block-based designs by eliminating the often time-consuming system re-optimization process that typically follows design changes and additions.
These two architectural advances give you the technology to freely add, modify, and move various portions of your design without negatively affecting design performance.
Sufficient Clock Networks
The MultiTrack interconnect structure is complemented by an advanced, low-skew clock network for clock distribution within the device. Stratix II GX devices provide 16 dedicated global clock networks (GCLKs) that span the entire device, and 32 regional local clock (LCLKs) networks.
The global clock networks span the entire general-purpose logic array, feeding all architectural structures and signals. Additionally, you can use global clocks for other device-wide signals with large fan-outs such as asynchronous clears and clock enables. The local clock networks provide the shortest paths with the least amount of skew within the quadrant, making them ideal for localized functions.
In addition to the clock networks described above, Stratix II GX gigabit transceiver blocks feature separate clock distribution resources that directly connect to the clocking resources of the device logic array. This architecture ensures maximum flexibility for reference clock generation, clock domain translation, and multi-channel functionality.
Figure 2. Illustration of Stratix II GX Clock Distribution
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