Differences Between the Stratix GX & Stratix II GX Transceivers
Stratix® II GX device transceivers build on the success, reliability, low power, and jitter performance of the Stratix GX device transceivers to provide a robust solution for many of the new applications emerging today. The transceivers integrate both an enhanced analog physical medium attachment (PMA) block and digital physical coding sub-layer (PCS) block. The PMA includes technology to aid signal integrity, reducing PCB layout risk. The PCS integrates dedicated features to reduce the FPGA overhead when supporting a number of key protocols.
Differences Within the PMA
The key difference between Stratix GX and Stratix II GX transceivers is the data rate. The Stratix II GX transceiver provides a native data range of 600 Mbps to 6.375 Gbps, while again supporting data rates as low as 270 Mbps with over-sampling. The data range was specifically chosen to support the majority of current and planned protocols and applications suitable for FPGAs. This targeted approach allows Altera to provide the optimum transceiver with exceptional jitter performance, but with the lower power consumption expected for backplane and inter-chip communication applications.
Support for data rates beyond 3.125 Gbps require specialist features in the transceiver to ensure successful data transmission, particularly if a higher data rate is to be achieved within an existing system. The Stratix II GX transceiver provides high levels of pre-emphasis and equalization with granular control to address this. Tools are available to simplify selection.
Stratix II GX FPGAs provide considerably more logic, memory, and digital signal processing (DSP) functionality than Stratix GX FPGAs in addition to the higher data rate transceivers. It is therefore necessary to provide more I/O circuitry for memory interfacing and high-speed source-synchronous LVDS signaling to cater for the increased complexity and the higher bandwidth from the transceivers. The increased number of I/O pins has led to significant efforts to manage simultaneous switching noise (SSN). Stratix II GX transceivers adopt a number of techniques to manage output SSN including a higher power and ground to I/O pin ratio combined with carefully designed packages.
Figure 1 shows the key differences between Stratix GX and Stratix II GX transceivers.
| Table 1. Stratix II GX and Stratix GX PMA Feature Comparison |
| Features |
Device |
| Stratix GX |
Stratix II GX |
| Data Rate Range |
500 Mbps – 3.1875 Gbps |
600 Mbps – 6.375 Gbps |
Data Rate Range
With Over-Sampling |
270 Mbps – 3.1875 Gbps |
270 Mbps – 6.375 Gbps |
| Typical Power Consumption |
150 mW/Channel @ 3.1875 Gbps |
125 mW/Channel @ 3.1875 Gbps (1)
225 mW/Channel @ 6.375 Gbps |
| Maximum Pre-Emphasis Level |
140% (2)
2 Taps |
500% (2)
3 Taps |
| Maximum Equalization |
9 dB
1 Stage
4 Levels |
17 dB
4 Stages
16 Levels |
| Output Differential Voltage Range |
400 mV – 1600 mV |
400 mV – 1400 mV |
Notes:
- Based on test chip characterization Maximum value based on 400 mV VOD.
- Max value will vary with VOD setting.
Differences Within the PCS
The Stratix II GX PCS includes a number of unique features to support key industry protocols including the PCI Express, Common Electrical Interface 6-Gbps (CEI-6G), serial digital interface (SDI), XAUI, SONET, Gigabit Ethernet, Serial RapidIOTM, and SerialLite II standards. The features, which are utilized by the Altera high-speed protocol portfolio, means that in the majority of cases, the physical layer of the protocol can be handled within the transceiver block without the need of FPGA logic.
Other key enhancements to the Stratix II GX transceiver block include a more flexible and functional phase-locked loop (PLL) design. The Stratix II GX transceivers are organized in quads similar to Stratix GX transceivers, however Stratix II GX now provides two PLLs per quad, each with a number of outputs. This means that all the transceivers within the Stratix II GX transceiver can run at different data rates, providing rates that are a function of the original clock frequencies into the transmitter PLLs. Stratix II GX transceivers continue to offer dynamic control of key signal integrity settings for pre-emphasis, equalization, and VOD. In addition, Stratix II GX transceivers enable the user to change one transceiver's PLL and protocol settings, while the other transceivers in the quad continue to operate.
The Stratix II GX transceiver also adds dedicated blocks for bit and byte ordering within the transceiver block, reducing FPGA overhead when supporting other SDH/SONET protocols. Further enhancements have also been made to the 8b/10b encoders, rate matchers, and internal state machines delivering PCS compliance to the PCI Express, Gigabit Ethernet, and XAUI protocols. Figure 2 provides a snapshot of differences between the Stratix II GX PCS and the Stratix GX PCS.
| Table 2. Stratix II GX and Stratix GX PCS Feature Comparison |
| Features |
Device |
| Stratix GX |
Stratix II GX |
| Channel Groups |
Quad (4 RX PLLs / 1 TX PLL)
Independent Channels
One Data Rate Per Quad |
Quad(4 RX PLLs / 2 TX PLLs)
Independent Channels
Individual Data Rate Per Channel |
| Number of Channels |
4 to 20 |
4 to 20 |
| Encoding |
8b/10b |
8b/10b |
| Dynamic Reconfiguration |
Pre-Emphasis
Equalization
VOD |
Stratix GX Features + PLL Definition
Protocol Settings |
| Bit Reordering |
No
(must be designed in FPGA fabric) |
Yes |
| Byte Reordering |
No
(must be designed in FPGA fabric) |
Yes |
FPGA
Transceiver Interface |
8 bit, 10 bit, 16 bit, 20 bit |
8 bit, 10 bit, 16 bit, 20 bit, 32 bit, 40 bit |
Stratix GX Series FPGAs
Stratix GX and Stratix II GX transceivers provide complete coverage for customers requiring an FPGA with integrated transceiver. The Stratix GX transceiver continues to be an ideal solution for customers requiring a low logic element (LE) to transceiver ratio, while the Stratix II GX transceiver is ideal for higher-end applications requiring more logic or increased performance and integration. Figure 1 shows the Stratix GX series fit.
Figure 1. Stratix GX Series Fit
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