Nios Embedded Processors in Stratix II GX
The Nios® II family of embedded processors is based on the highly successful first-generation Nios processor and delivers three processor cores to address an even wider range of embedded processing applications. Designers can choose from three Nios II family members: Nios II/f (fast, optimized for maximum performance), Nios II/e (economy, optimized for cost), and Nios II/s (standard, balanced between performance and cost). The Nios II family of processors addresses tasks such as:
- Implementing complex state machines
- Off-loading existing processors
- Performing I/O and data-processing tasks
- Configuring FPGAs remotely
- Accelerating digital signal processing (DSP) algorithms
The combination of the advanced architectural features of Stratix® II GX FPGAs and the enhanced performance of Nios II embedded processors offers the processing power required for today's high-bandwidth systems. With up to 132,540 logic elements (LEs) available in the largest Stratix II GX devices, multiple Nios II processors can easily fit into a single Stratix II GX device, which satisfies the needs of networking, telecommunications, mass storage, and DSP applications. Figure 1 shows an example of multiple Nios II processors within a single Stratix II GX FPGA in a packet-processing networking design.
Figure 1. Nios II Processors in a Stratix II GX Device for I/O Processing
Notes:
- MAC = Media access control
- DMA = Direct memory access
FPGA Device Architecture
The Stratix II GX FPGA logic structure has been enhanced to allow it to perform certain frequently used functions efficiently, such as implementing 2 x 4:1 multiplexers in the equivalent of two LEs, compared with four in previous architectures. This works well with system blocks such as the Avalon™ interconnect fabric. The Stratix II GX FPGA’s wide input function support means that as the system increases in complexity, the performance penalty will also be reduced.
The Nios II processor includes several CPU-optimization options, which allow it to benefit from the Stratix II GX device’s DSP blocks, which can implement a single cycle-multiply function in a single DSP block. This implementation can save 370 LEs and hundreds of clock cycles when compared to a soft implementation. In the same way, the Stratix II GX FPGA adaptive logic modules (ALMs) ternary adder support further reduces the size of the Nios CPU’s arithmetic logic unit (ALU).
The embedded DSP blocks in the Stratix II GX device architecture also provide the perfect complement to Nios II custom instructions and other hardware acceleration units. DSP designers can now create DSP algorithms and complex math routines in high-performance hardware DSP blocks and access them as regular software routines or implement them as custom instructions to the Nios CPU. For example, in a voice-over-IP (VOIP) application, an echo-cancellation algorithm can be implemented in hardware and directly executed in software using a custom instruction. This gives designers the flexibility and portability of high-level software design while maintaining the performance benefits of parallel hardware operations in FPGAs—without resorting to excessive clock speeds.
The Stratix II GX device's TriMatrix™ memory caters to all the memory needs of a typical system-on-a-programmable-chip (SOPC) system. TriMatrix memory is composed of three sizes of embedded RAM blocks, including 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit M-RAM blocks, each of which can be configured to support a wide range of features. A high memory-to-logic ratio makes Stratix II GX devices ideal for embedded applications requiring extensive accessibility to the memory resources.
The Nios II processors also feature instruction and data caching. Users can add instruction or data caches sized from 512 bytes to 64 Kbytes. The abundant TriMatrix memory blocks can implement on-chip cache memory for accelerating off-chip memory access and significantly increasing overall software performance in embedded systems.
Stratix II GX Devices & Nios II Processors: A Complete SOPC Solution
The Stratix II GX architecture is ideal for the block-based design methodology that is required for designing large systems using pre-optimized intellectual property (IP) modules or re-using existing design modules.
Altera's SOPC Builder automated system development tool provides designers with a powerful platform for composing bus-based systems out of common system components such as processors, peripherals, and memory interfaces. SOPC Builder-generated systems (such as the one shown in Figure 2) are pre-optimized IP blocks that benefit significantly from the Stratix II GX architecture.
Figure 2. Typical SOPC Builder-Generated System
A Stratix II GX designer can use SOPC Builder to add system components without any substantial impact on system performance; this is possible because of Quartus® II software's LogicLock™ design methodology feature. SOPC Builder also creates a simulation environment with a testbench for the customer hardware, and can be used to launch the Nios II integrated development environment (IDE).
SOPC Builder provides many customizable peripherals that enable designers to create a completely functional system from a concept in minutes. These peripherals include:
- Interrupt controllers
- Direct memory access (DMA)
- Parallel I/O blocks
- Serial interfaces
- Memory interfaces
The Nios II IDE is a complete software development environment that handles all software development tasks, such as program editing, compiling, and debugging.
The Nios II peripherals and interfaces web page has more details on the peripherals available for the Nios II processors.
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