Stratix® II GX FPGAs offer a robust solution to high-speed serial connectivity with transceivers that deliver best-in-class signal integrity. Stratix II GX transceivers include both a physical coding sublayer (PCS) and a physical media attachment sublayer (PMA), and are architected to deliver excellent jitter performance and minimize power, cost, and simultaneous switching noise (SSN).
The PMA functionality, implemented in analog circuitry, includes:
- Programmable pre-emphasis and equalization
- Clock data recovery (CDR)
- Serializer/deserializer (SERDES)
- I/O buffers
Figure 1 shows the PMA subsection of a transceiver.
Figure 1. Stratix II GX Transceiver PMA Subsection
Programmable Pre-Emphasis and Equalization Reduce Cost and Increase Signal Integrity
Using pre-emphasis and equalization in Stratix II GX devices reduces board cost by minimizing the need for expensive board material and layout techniques. Low-cost FR-4 PCB fabric tends to attenuate the high-frequency components of fast edge-rate signals. At around 6 Gbps, the effect is severe and can cause the signal eye to disappear entirely, resulting in data loss.
Stratix II GX devices offer both pre-emphasis and equalization to overcome these losses and increase signal integrity. You can configure the pre-emphasis circuit to a number of different levels, depending on the system requirement, shaping the waveform to improve the high-frequency signal. Stratix II GX devices also offer a wide (17 dB) range of dynamic equalization to help overcome board losses as signals are attenuated at the receiver. You can configure equalization to one of 16 levels, depending on system requirements.
Both pre-emphasis and equalization can be changed either while the system is running or when configuring a card after it is inserted into the backplane. These features can also be used during field trials for system setup and to confirm simulation results. Figure 2 shows how pre-emphasis greatly improves signal integrity in a 6.375-Gbps near-end eye diagram.
Figure 2. 6.375-Gbps Near-End Eye Diagram
This unprecedented flexibility puts you in control of the system, allowing you to make design decisions that reduce costs and increase signal integrity.
Support for CDR-Based Bus Standards
Each receiver CDR block has a unique phase-locked loop (PLL) to allow the data to be received correctly and to correct skew between the channels caused by the transmission line where more than one transceiver is required for a particular protocol. The CDR extracts the clock from the incoming serial data stream and provides a recovered clock that samples the serial data stream clocks the deserializer. Stratix II GX transceivers provide CDR to support bus standards such as PCI Express, serial digital interface (SDI), XAUI, SONET, Gigabit Ethernet, Serial RapidIO™ (SRIO), SerialLite II, and CEI-6G standards.
Flexible Transceiver PLLs & Clocking Modes
Stratix II GX FPGAs arrange transceivers in a quad implementation. Each quad can be driven by two different clock sources, each with access to a high-speed and a low-speed PLL. The combination of clocks and PLLs supports four different data rates within a single quad, which allows the quad to support four different protocols if required. The dual-quad architecture dramatically reduces power dissipation compared to the single-PLL implementation found in competing devices.
Differential I/O Buffer Supports 1.5-V PCML I/O Standard
The Stratix II GX device buffers have a dynamically controllable VOD setting, which allows you to select the desired level while the transceiver is running. For example, dynamically reconfigurable programmable pre-emphasis and equalization capabilities tailor the data signal to compensate for signal degradation across the transmission medium. A variety of programmable VOD settings ensure that the drive strength aligns with the line impedance and trace length. Additionally, differential on-chip termination provides the appropriate receiver and transmitter buffer termination for moderate-performance signals.
Architected for Low Power
Transceivers are often used in backplane and inter-board connectivity where cooling is difficult to manage. Therefore, it is important for the transceiver to have minimal power consumption. The Stratix II GX transceiver is architected to support a targeted data range meeting the “sweet spot” of applications and protocol requirements. This targeted approach, combined with an optimized data path and clocking, means that the transceivers within Stratix II GX FPGAs use less than half the power of their nearest FPGA competitor. This can be a considerable power savings, as many applications require a number of transceivers to meet requirements.
Optimized for Minimal SSN
High-speed I/O and wide high-speed bus interfaces require designers to minimize simultaneous switching noise (SSN) to achieve high signal integrity.
Stratix II GX devices are built on the Stratix II FPGA package design, which delivers extremely high immunity to SSN. The Stratix II GX device adopts an aggressive signal-power-ground pin ratio to minimize SSN effects and to account for the embedded transceivers. This ensures Stratix II GX devices provide an extremely robust SSN solution.
