Stratix II GX FPGA Overview
Stratix® II GX FPGAs are specifically architected to meet the full system demands of both current and future serial I/O-based applications. Stratix II GX devices fuse the industry's fastest and highest-density FPGA architecture with up to 20 full-duplex, high-performance, multi-gigabit transceivers. The transceivers deliver excellent jitter performance across the entire 600-Mbps to 6.375-Gbps operating range. When used with the multiple levels of dynamic pre-emphasis and equalization, they provide a low-risk design path for both new system and legacy system design applications.
Stratix II GX devices include specific hard intellectual property (IP) within the transceiver block to support many key protocols, including the PCI Express, Common Electrical Interface 6 Gbps (CEI-6G), serial digital interface (SDI), XAUI, SONET, Fibre Channel, Gigabit Ethernet, Serial RapidIOTM, and SerialLite II standards. The blocks may also be bypassed, providing solutions for custom transceiver applications.
As with Stratix GX devices, the transceivers have been optimized to provide a low-power solution, which is particularly important in backplane applications where cooling can be difficult. Table 1 highlights the features and benefits of Stratix II GX FPGAs.
| Table 1. Stratix II GX Transceiver FPGAs Features Summary |
| Feature |
Description |
| Excellent Signal Integrity |
The transmitter has low jitter generation and up to 500 percent pre-emphasis. The receiver has excellent jitter tolerance, and up to 17-dB equalization, which can either be continuously and automatically adjusted by an on-chip controller, or set statically. |
| Low Power |
The transceiver dissipates 225 mW per channel at 6.375 Gbps, and only 125 mW per channel at 3.125 Gbps. |
| PCS Support (Hard IP) |
The transceiver supports the following PCS blocks: PCI Express, PIPE-Compliant PCS, CEI-6G-LR/SR, 8b/10b encoder/decoder, XAUI state machine and channel bonding, Gigabit Ethernet state machine, SONET, and 8b/10b and 8/10/16/20/32/40-bit interface (to FPGA logic). |
| System-Level Diagnostics |
Serial loopback, reverse serial loopback, pseudo-random binary sequence (PRBS) generator and checker, and the registered-based interface facilitate dynamic reconfiguration of pre-emphasis, equalization, and differential output voltage. |
Based on a 1.2-V, 90-nm, SRAM process, Stratix II GX devices are available in densities ranging from 33,880 to 132,540 equivalent logic elements (LEs), with over 6.7 Mbits of on-chip RAM and up to 252 (18-bit x 18-bit) embedded multipliers provided in highly optimized digital signal processing (DSP) blocks.
In addition to the high-speed serial transceivers, Stratix II GX devices can provide up to 76 source-synchronous differential signaling I/O pins with dedicated dynamic phase alignment (DPA) circuitry operating at up to 1 Gbps. The I/O pins also have dedicated serializer/deserializer (SERDES) circuitry to support the LVDS and HyperTransport™ differential I/O electrical standards, and support high-speed communication interfaces—including the 10-Gigabit Ethernet XSBI, SFI-4, SPI-4.2, HyperTransport, RapidIO, and UTOPIA IV standards.
With up to 8 phase-locked loops (PLLs) and 16 global clock networks, Stratix II GX FPGAs offer a complete clock management solution, including a hierarchical clock structure. In addition, Stratix II GX devices offer design security, on-chip termination, and remote system upgrade capabilities. Table 2 outlines the Stratix II GX devices and features. Table 3 details the Stratix II GX transceiver, device packages, and maximum user I/O pins.
| Table 2. Stratix II GX Device Features (1) |
| Feature |
Device |
| EP2SGX30C/D |
EP2SGX60C/D/E |
EP2SGX90E/F |
EP2SGX130G |
| Transceiver Data Rate |
600 Mbps–6.375 Gbps |
| Adaptive Logic Modules (ALMs) (2) |
13,552 |
24,176 |
36,384 |
53,016 |
| Equivalent LEs (2) |
33,880 |
60,440 |
90,960 |
132,540 |
| LVDS Channels |
29 |
29 |
45 |
78 |
| M512 RAM Blocks |
202 |
329 |
488 |
699 |
| M4K RAM Blocks |
144 |
255 |
408 |
609 |
| MRAM Blocks |
1 |
2 |
4 |
6 |
| Total RAM Bits |
1,369,728 |
2,544,192 |
4,520,448 |
6,747,840 |
| DSP Blocks |
16 |
36 |
48 |
63 |
| Embedded Multipliers (3) |
64 |
144 |
192 |
252 |
| PLLs (4) |
4 |
4/4/8 |
8 |
8 |
| Device Availability |
Buy Now |
Buy Now |
Buy Now |
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Notes:
- Features are preliminary and subject to change.
- Each ALM is equivalent to 2.5 LEs.
- Each DSP block in Stratix II GX devices can implement four 18×18 multipliers or one 36×36 multiplier. To obtain the total number of 36×36 multipliers per device, divide the total number of 18×18 multipliers by a factor of 4.
- Includes both enhanced PLLs and fast PLLs.
| Table 3. Stratix II GX Transceiver, Device Packages, and Maximum User I/O Pins (1, 2) |
| Device |
Transceiver Channels |
LVDS Channels |
Device Package and User I/O |
| Receive |
Transmit |
F780 (29 mm) User I/O Pins |
F1152 (35 mm) User I/O Pins |
F1508 (40 mm) User I/O Pins |
| EP2SGX30C |
4 |
31 |
29 |
361 |
— |
— |
| EP2SGX60C |
4 |
31 |
29 |
364 |
— |
— |
| EP2SGX30D |
8 |
31 |
29 |
361 |
— |
— |
| EP2SGX60D |
8 |
31 |
29 |
364 |
— |
— |
| EP2SGX60E |
12 |
42 (3) |
42 |
— |
534 |
— |
| EP2SGX90E |
12 |
47 (3) |
45 |
— |
558 |
— |
| EP2SGX90F |
16 |
59 (3) |
59 |
— |
— |
650 |
| EP2SGX130G |
20 |
73 (3) |
71 |
— |
— |
734 |
Notes:
- The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock-reference pins for high-speed I/O capability.
- User I/O counts are preliminary and subject to change.
- Includes two differential clock inputs that can also be used for two additional channels for the differential receiver.
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