Stratix® II GX FPGAs are specifically architected to meet the full system demands of both current and future serial I/O-based applications. Stratix II GX devices fuse the industry's fastest and highest density FPGA architecture with up to 20 full-duplex, high-performance, multi-gigabit transceivers. The transceivers deliver excellent jitter performance across the entire 600-Mbps to 6.375-Gbps operating range. When used with the multiple levels of dynamic pre-emphasis and equalization, they provide a low-risk design path for both new system and legacy system design applications.
Table 1 highlights the features and benefits of Stratix II GX FPGA transceivers. Table 2 outlines Stratix II GX devices and features. Table 3 details the Stratix II GX transceiver, device packages, and maximum user I/O pins. Table 4 shows industrial temperature support for Stratix II GX FPGAs.
| Table 2. Stratix II GX FPGA Features (1) | ||||
| Feature | Device | |||
|---|---|---|---|---|
| EP2SGX30C/D | EP2SGX60C/D/E | EP2SGX90E/F | EP2SGX130G | |
| Transceiver Data Rate | 600 Mbps–6.375 Gbps | |||
| Adaptive Logic Modules (ALMs) (2) | 13,552 | 24,176 | 36,384 | 53,016 |
| Equivalent LEs (2) | 33,880 | 60,440 | 90,960 | 132,540 |
| LVDS Channels | 29 | 29 | 45 | 78 |
| M512 RAM Blocks | 202 | 329 | 488 | 699 |
| M4K RAM Blocks | 144 | 255 | 408 | 609 |
| M-RAM Blocks | 1 | 2 | 4 | 6 |
| Total RAM Bits | 1,369,728 | 2,544,192 | 4,520,448 | 6,747,840 |
| DSP Blocks | 16 | 36 | 48 | 63 |
| Embedded 18-Bit x 18-Bit Multipliers (3) | 64 | 144 | 192 | 252 |
| PLLs (4) | 4 | 4/4/8 | 8 | 8 |
| Availability | Buy Now | Buy Now | Buy Now | Buy Now |
- Features are preliminary and subject to change.
- Each ALM is equivalent to 2.5 LEs.
- Each DSP block in Stratix II GX devices can implement four 18×18 multipliers or one 36×36 multiplier. To obtain the total number of 36×36 multipliers per device, divide the total number of 18×18 multipliers by a factor of 4.
- Includes both enhanced PLLs and fast PLLs.
| Table 3. Stratix II GX Transceiver, Device Packages, and Maximum User I/O Pins (1, 2) | ||||||
| Device | Transceiver Channels | LVDS Channels | Device Package and User I/O | |||
|---|---|---|---|---|---|---|
| Receive | Transmit | F780 (29 mm) User I/O Pins | F1152 (35 mm) User I/O Pins | F1508 (40 mm) User I/O Pins | ||
| EP2SGX30C | 4 | 31 | 29 | 361 | — | — |
| EP2SGX60C | 4 | 31 | 29 | 364 | — | — |
| EP2SGX30D | 8 | 31 | 29 | 361 | — | — |
| EP2SGX60D | 8 | 31 | 29 | 364 | — | — |
| EP2SGX60E | 12 | 42 (3) | 42 | — | 534 | — |
| EP2SGX90E | 12 | 47 (3) | 45 | — | 558 | — |
| EP2SGX90F | 16 | 59 (3) | 59 | — | — | 650 |
| EP2SGX130G | 20 | 73 (3) | 71 | — | — | 734 |
- The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock-reference pins for high-speed I/O capability.
- User I/O counts are preliminary and subject to change.
- Includes two differential clock inputs that can also be used for two additional channels for the differential receiver.
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