The Stratix® II GX FPGA provides a strong solution for the growing number of applications and protocols requiring multi-gigabit serial I/O. The Stratix II GX FPGA transceiver architecture provides robust noise immunity and excellent jitter performance across an operating range of 600 Mbps to 6.375 Gbps, while maintaining the lowest power consumption. Stratix II GX FPGAs, available in production today, are built using the industry’s fastest and highest-density Stratix II FPGA fabric and integrate up to 20 serializer/deserializer (SERDES)-based transceivers.
Best-In-Class Signal Integrity
Stratix II GX FPGA transceiver architecture successfully operates at data rates up to 6.375 Gbps on transmission lines to 50" (1.25 m) in length, on boards and backplanes fabricated on standard FR-4 material, and up to 30 m of PCIe cable at 2.5 Gbps. To achieve this, the transceivers include a number of features to ensure signal integrity at these higher data rates, while maintaining low power. These include:
- Plug & Play Signal Integrity with the industry’s first adaptive equalizer – Altera’s adaptive dispersion compensation engine (ADCE)
- Physical medium attachment (PMA) layer with dynamically selectable signal integrity features (including phase-locked loop (PLL) architecture)
- Transceiver dynamic reconfiguration to support multiple protocols, data rates and physical medium attachment (PMA) settings
- Optimized circuitry to deliver less than half the power requirement of nearest competitor
Complete Protocol Solution
The Stratix II GX FPGA is part of a complete solution to key protocols used in many of today’s high-speed serial applications. Support is provided for PCI Express, CEI-6G, serial digital interface (SDI), Gigabit Ethernet, Serial RapidIO® (SRIO), XAUI, SerialLite II, Fibre Channel, and SONET standards. The complete solution includes:
- Dedicated physical coding sublayer (PCS) protocol circuitry
- Optimized protocol intellectual property (IP) from Altera and AMPPSM Partners
- Protocol-specific characterization, collateral, and reference designs
- Protocol-specific development kits
Innovative Logic Structure
The Stratix II GX FPGA is built on the innovative adaptive logic module (ALM) logic structure found in the Stratix II FPGA, using TSMC's 90-nm, low-k dielectric process technology, optimized to maximize performance and control power leakage. A Stratix II GX FPGA can provide up to 20 high-speed serial transceivers and up to 130 K equivalent logic elements (LEs), 6.7 Mbits of embedded memory with up to 252 (18-bit x 18-bit) multipliers for efficient implementation of high-performance filters and other digital signal processing (DSP) functions. Key features of the Stratix II GX FPGA architecture include:
- A rich feature set including high-performance DSP blocks and on-chip memories
- High-speed I/O pins using dynamic phase alignment (DPA) circuitry
- External memory interfaces
- Clock management solution
- Design security
Design With Confidence Today
All Stratix II GX devices are shipping in production volume to customers. The following resources are now available from Altera and ecosystem partners to get you started designing with an Altera® Stratix II GX FPGA:
- Download Stratix II GX Literature and Utilities including:
- Design Software Tools and IP Evaluations
- Stratix II GX Signal Integrity Development Kit supporting:
- Signal integrity evaluation
- System interoperability testing
- System design
- Stratix II GX Signal Integrity Tools including:
- SPICE simulation models, Link Estimators, and third-party simulation tool models and design kits
- Stratix II GX Characterization
- Stratix II GX Eye Diagram Viewer Online Characterization Tool
Informative webcasts providing hints and tips on signal Integrity
