Stratix II vs. Virtex-4 Open Core Density Benchmark
Publicly available open core designs provide a good comparison of FPGA densities. A total of 25 of these open core designs, obtained from www.opencores.org, were used to benchmark Stratix® II and Virtex-4 density. The open core density benchmark result is the same as the result obtained by benchmarking real customer designs. It provides further proof that designers can fit more logic in a Stratix II FPGA than a similarly named Virtex-4 device. Figure 1 shows a Stratix II versus Virtex-4 logic density comparison based on the density benchmark result.
Figure 1. Stratix II vs. Virtex-4 Logic Density Comparison
Open Core Benchmark Details
The 25 open core designs were selected based on their popularities and they are all written in generic hardware description languages (HDLs). To provide a fair comparison, no manual optimization of the design code is done except for getting the designs to compile and making the RAM modules to target both FPGA architectures. The designs are synthesized using Synplify Pro software version 8.0 and compiled using Quartus® II software version 5.0 or ISE software version 7.1i service pack 1. Similar to the customer design benchmark, the open core designs are compiled for minimum area while targeting fixed performance. Figure 2 shows the result of the open core density benchmark.
Figure 2. Stratix II ALM vs. Virtex-4 Slice Open Core Benchmark
The adaptive logic module (ALM) is the basic logic structure of Stratix II while the slice is the basic logic structure of Virtex-4. The open core density benchmark result shows that, on average, one Stratix II ALM is equivalent to 1.3 Virtex-4 slices and, therefore, designers can fit more logic in Stratix II than Virtex-4. This is the same as the result obtained through the real customer design benchmark.
Run Your Own Density Benchmark
Designers can make their own density comparison using the publicly available open core designs. For Stratix II, use the Quartus II area optimization settings shown in Table 1.
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Table 1. Quartus II Area Optimization Options
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Options
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Setting
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Perform WYSIWYG Resynthesis
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On
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Optimization Technique
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Area
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Restructure Multiplexers
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On
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Auto Packed Registers
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Minimize Area With Chains
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