Stratix II DSP Blocks
Stratix® II and Stratix II GX devices offer features such as DSP blocks, TriMatrix™ memory, and adaptive logic modules (ALMs) that are optimized for high-performance digital signal processing (DSP) applications. Stratix II devices are ideal for applications such as video and image processing and high-speed digital communications.
When combined with TriMatrix memory and ALMs, DSP blocks can efficiently implement DSP algorithms such as filtering, video and image processing, scaling, chip-rate processing, equalization, digital downconversion / digital upconversion (DDC/DUC), transforms, and modulation.
Stratix II and Stratix II GX DSP blocks are capable of running at 450 MHz and provide very high DSP throughput (up to 346 GMACs) that is orders of magnitude higher than competing DSP processors available today. Using DSP blocks, Stratix II FPGAs can easily meet the DSP throughput requirements of emerging standards and protocols such as JPEG 2000, H.264, WM9, CDMA2000, 1x EV DV, HSDPA, W-CDMA and WiMAX as shown in Table 1. Stratix II GX devices additionally provide high-speed transceivers (operating at up to 6.5 Mbps) to allow the implementation of SDI.
| Table 1. DSP Applications that Can Be Implemented Using DSP Blocks |
| Applications |
Military Applications |
Image Processing |
Communications |
| Radar/Sonar |
Broadcast & Medical |
Wireless |
| Algorithms & Functions |
- Filtering
- Transforms
- Modulation
|
- Filtering
- Color Space Conversion
- Scaling
|
- Chip-Rate Processing
- Equalization
- Digital IF (DDC, DUC)
|
| Standards & Protocols |
- |
|
- HSDPA
- CDMA 2000, 1x EV DV
- WiMAX (802.16d/e)
|
DSP Block Details
The DSP block architecture has been optimized for implementing several DSP functions with maximum performance and minimum logic resource utilization. Each DSP block offers multipliers, adders, subtractors, accumulators and a summation unit—functions that are frequently required in typical DSP algorithms. Figure 1 shows the DSP block architecture.
Figure 1. DSP Block Architecture
Each DSP block can support a variety of multiplier bit sizes (9x9, 18x18, 36x36) and operation modes (multiplication, complex multiplication, multiply-accumulation and multiply-addition), and can offer a DSP throughput of 3.6 giga multiply-accumulate operations per second (GMACS) per DSP block. The largest Stratix II device, the EP2S180 device, has 96 DSP blocks that offer a throughput of 346 GMACS and can support up to 384 18x18 multipliers. The throughput in Stratix II devices is orders of magnitude higher than single-chip DSP processors available in the marketplace today.
In addition, new rounding and saturation support has been added to the DSP block to facilitate porting DSP firmware code onto the FPGA. Many applications, such as speech processing, use rounding and saturation due to the fixed widths of the memory buffers that store the data. Earlier, digital signal processor designers using fixed-point numbers and FPGAs had to modify their design to accommodate rounding and saturation. With the rounding and saturation support in DSP blocks, it is now much easier to port DSP-processor-based designs to an FPGA implementation.
The latest Quartus® II software has been further optimized for mapping signal processing algorithms onto the Stratix II DSP block architecture.
For more details on the DSP block feature, refer to the Stratix II Device Family Data Sheet (PDF) in the Stratix II Device Handbook.
DSP Co-Processing With Stratix II FPGAs
Stratix II FPGAs can be used to implement complete DSP systems that require high DSP throughput. They can also be used as FPGA co-processors in DSP applications for accelerating performance-critical DSP functions—these functions would otherwise consume a majority of the host processors processing power and slow down overall system performance. Stratix II FPGA-based co-processors can boost overall system performance by offloading complex computations such as turbo decoding, echo cancellation, multi-user detection, and correlators from the host processor.
Video and Image Processing With Stratix II FPGAs
For video and image processing applications, Altera have created the Video & Image Processing Suite. This suite contains a set of 9 IP MegaCores® that can be used separately or combined to provide a solution to all your image processing requirements.
Altera offers designers a broad range of support services, tools, and development platforms for implementing DSP designs in Stratix II FPGAs. User-defined FPGA co-processors can be developed quickly with DSP Builder, Altera’s data flow architecture development tool based on The MathWorks’ industry-leading MATLAB and Simulink tools. Once the co-processor architecture is captured, it can automatically be implemented into an Altera® FPGA or exported to Altera’s SOPC Builder system development tool for further integration into the overall system architecture.
Altera also offers DSP and Video oriented development kits that can be used to verify your systems in hardware in the prototype phase of your design cycle.
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