Stratix II Clock Management Circuitry
With up to 12 phase-locked loops (PLLs) and a hierarchical clocking scheme providing up to 48 unique clock domains per device, Altera® Stratix® II devices are built to function as the central clock manager to meet system timing challenges. Based on the successful Stratix device architecture, Stratix II devices offer advanced on-chip PLL features such as spread-spectrum clocking, clock switchover, programmable frequency synthesis, programmable delay shift, programmable phase shift, external feedback, and programmable bandwidth. Stratix II devices offer PLL reconfiguration, allowing users to change the PLL configuration without reprogramming the entire device. In addition, Stratix II fast PLLs also support the dynamic phase alignment (DPA) feature that can dynamically correct channel-to-channel skew in high-speed system. Stratix II PLLs increase system and device performance and provide advanced clock interfacing and clock-frequency synthesis.
Figure 1 shows a block diagram of the Stratix II PLL.
Figure 1. Stratix II PLL Block Diagram
Altera Stratix II devices have two types of PLLs: enhanced and fast PLLs. Enhanced PLLs are feature-rich, general-purpose PLLs supporting advanced features such as external feedback, clock switchover, PLL reconfiguration, spread-spectrum clocking, and programmable bandwidth. Fast PLLs are optimized for high-speed differential I/O interfaces and offer features such as DPA. Fast PLLs can also be used for general-purpose PLL clocking. Table 1 outlines the enhanced and fast PLL features found in Stratix II devices.
| Table 1. Stratix II PLL Features |
| Features |
Enhanced PLL |
Fast PLL |
| InputFrequencyRange |
1.5–450 MHz |
20–750 MHz |
| Output Frequency Range |
1.5–500 MHz |
9.375 MHz to 1.040 GHz |
| External Output Frequency Range |
1.5–450 MHz |
1.5–500 MHz |
| Programmable Frequency Synthesis |
Yes |
Yes |
| Programmable Phase Shift |
125 ps |
105 ps |
| Programmable Delay Shift |
125 ps |
105 ps |
| Clock Switchover |
Yes |
Yes |
| PLL Reconfiguration |
Yes |
Yes |
| Programmable Bandwidth |
Yes |
Yes |
| Clock Power Down Mode |
Yes |
Yes |
| Dynamic Clock Source Select |
Yes |
Yes |
| Dynamic Phase Alignment (DPA) Support |
No |
Yes |
| Spread-Spectrum Clocking |
Yes |
No |
| Number of Dedicated External Differential Clock Outputs |
3 (1) |
0 |
| Number of Feedback Clock Inputs |
1 |
0 |
| Number of PLLs per Device |
Up to 4 |
Up to 8 |
Note:
- Every enhanced PLL can support six external single-ended or three external differential outputs.
System-Level Clock Management
Each Stratix II device has up to four enhanced PLLs with dedicated outputs to manage board-level system timing. There are up to 24 single-ended or 12 differential outputs. These outputs can provide clocks to other devices in the system, eliminating the need for other clock sources on the board. Users can utilize a combination of the features provided in the Stratix II PLLs, such as programmable phase shift, external feedback, and delay to compensate for board-level skew and delays.
Clock Network
Each Stratix II device has up to 48 different clock networks. This web of high-speed clock networks, in combination with abundant PLLs, ensures that the most complex design can run at optimal performance and with minimum clocking skew.
|
 |
|
Literature
> 
