Test Market ASSPs with Secure Stratix II and Stratix II GX FPGAs
As semiconductors continue to move to smaller process geometries, ASSP vendors need to have a larger market in order to get a reasonable return on their ASIC investment. The flexibility and rich feature set of Stratix® II and Stratix II GX FPGAs along with the built-in configuration bitstream encryption (shown in Figure 1) allow ASSP vendors to test market products risk-free and expand their total available market by addressing niche opportunities.
Figure 1. Stratix II and Stratix II GX Design Security with Configuration Bitstream Encryption
The following are some of the key features of the Stratix II and Stratix II GX design security solution:
- Industry’s only high-performance, high-density FPGAs with non-volatile security
- Non-volatile encryption key storage (no battery back-up required)
- 128-bit AES encryption with FIPS-197 certification
- Socket programming service
ASSP vendors can ship Stratix II or Stratix II GX FPGAs containing security keys as ASSPs along with encrypted design files to their end customers. Since the encrypted design file only works with Stratix II or Stratix II GX FPGAs containing the correct key, ASSP vendors can maintain control of the intellectual property (IP). The non-volatility of the key is essential because it allows the security key to be programmed into the FPGA using socket programming without requiring the device to be soldered onto the board. This socket programming service can be provided by a trusted third party.
Key Applications of the Stratix II and Stratix II GX Design Security Feature for ASSP Vendors
The design security feature of Stratix II and Stratix II FPGAs offers ASSP vendors the benefits of reduced product development risk and R&D costs.
- Test market ASSP: The biggest risk to ASSP success is delivering functionality that does not meet the market’s need. Prior to committing millions of dollars to design and develop a complex ASIC, ASSP vendors can easily test market their products using Stratix II or Stratix II GX FPGAs while protecting their IP. Once the test market phase is complete, and the ASSP vendor is assured that the feature set has met the market requirements, further investments can be made to develop full custom ASICs. For designs with reasonably high volume but still not enough volume to justify full custom ASICs, Altera offers a seamless low-cost migration path from Stratix II FPGAs to HardCopy® II ASICs. Compared to standard cell ASICs, HardCopy II ASICs offer lower NRE and lower risk, and are functionally equivalent and pin-compatible with Stratix II FPGAs. Using this test market approach reduces product definition and development risks significantly.
- Expand market to niche opportunities: For niche markets that cannot justify the millions of dollars to do ASIC development, Stratix II and Stratix II GX FPGAs offer a flexible programmable logic solution without NRE. The reduction in R&D costs and faster time-to-market provided by Stratix II and Stratix II GX FPGAs allow ASSP vendors to target niche segments that may have previously been unattainable.
Contact Altera for More Information
The design security feature of Stratix II and Stratix II GX FPGAs allows ASSP vendors to test market their products using real hardware and serve a broader range of market segments in less time with less risk than conventional ASIC technology. HardCopy II ASICs provide both design security and low unit cost. To learn more about how to use the Stratix II and Stratix II GX design security feature and to obtain a copy of AN 341: Using The Design Security Feature in Stratix II Devices, please contact your local Altera sales representative.
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