ASIC Prototyping Design Style
Advantages of ASIC Prototyping In Stratix II
The primary goal of prototyping an ASIC in an FPGA is to determine the functionality of a design prior to committing the design to tape-out. Ideally, these requirements should have as little or no impact on the design flow as possible, and as few changes to the ASIC design as possible. The first of these is achieved by having FPGA design tools that integrate well into third-party EDA vendors' design flows and tools. The second requires the ability to take RTL that is well suited to the chosen ASIC architecture and target it to an FPGA without changes. In the past, with FPGA architectures being based on 4-input look-up tables (LUTs), this did not always produce satisfactory results in both area efficiency and speed of operation.
Stratix® II, the latest generation of Altera's full-featured FPGAs, provides the highest-density and highest-performance programmable logic devices available today. Stratix II implements a new logic structure called the Adaptive Logic Module (ALM). The ALM has 8 inputs into a shared LUT that feeds 1 or 2 registered or combinatorial outputs, in addition to a 3-input adder structure. By allowing more inputs into the LUT, fewer levels of logic are required to implement single functions of up to 7 inputs. By allowing a wider fan-in, fewer levels of logic are required to implement a wide input function, and so both performance and resource efficiency are increased. Figure 1 illustrates this for a 6-input function.
Figure 1. Reduced Average Resource Utilization
Typical ASIC structures do not limit the fan-in of a function. The ALM as a logic structure is more suited to HDL or RTL that is not targeted to 4-input LUTs, and will provide better performance with less logic utilization without the code having to be rewritten. This saves time and avoids the higher possibility for error created by writing the code twice (once for the ASIC and then for conversion to the FPGA architecture). See the Stratix II Design Building-Block Performance page for illustrations of the performance and logic utilization benefits.
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