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Power Consumption in Stratix II FPGAs

Home > Products > Devices > Stratix II (and GX) > Stratix II > Features > Power Consumption in Stratix II FPGAs

With Stratix® II FPGAs, you can accurately estimate power using the industry's most sophisticated FPGA power analysis tool, Quartus® II PowerPlay power analyzer. In addition, you can achieve the lowest dynamic power consumption, resulting in total device power that is equal to the nearest competing device. For technical details on Stratix II device power, comparisons against competiting FPGAs, and information on power estimation accuracy and management, refer to Table 1.

Table 1. Stratix II Device Power Resources
Technical Documentation
  • White Paper: Stratix II vs. Virtex-4 Power Comparison With Power Estimation Accuracy (PDF)
    • White Paper Summary: Stratix II vs. Virtex-4 Power Comparison Page
  • Overview of Quartus II PowerPlay Power Analysis & Optimization Technology
  • Quartus II Handbook Chapter, Power Optimization (PDF)
  • Stratix II 90-nm Silicon Power Optimization
Tools
  • Power Estimation Tools
  • Power Management Resource Center
    • Power Overview
    • Thermal Management
    • Power Supply Integrity
    • Power Supply Regulation
    • Power Partner Solutions

Quartus II PowerPlay—The Only Accurate Power Software

To select the correct thermal solution and power management components, accurate FPGA power estimation is essential. Altera’s Quartus II PowerPlay power analyzer provides estimates to within 20 percent error. Figure 1 compares the estimation results of designs that were compiled in Quartus II PowerPlay and ISE XPower with bench measurements of Stratix II and Virtex-4 FPGAs. The PowerPlay results are all within 20 percent of silicon, while XPower results generally show a significant spread.

Figure 1. Estimation Error of Dynamic Power for 20 Individual Designs From Quartus II PowerPlay & ISE XPower

Figure 1. Estimation Error of Dynamic Power for Individual Designs From Quartus II PowerPlay & ISE XPower

Note:
* The Xilinx ISE XPower tool crashes when reading large complex Value Change Dump (.vcd) files. No XPower estimates are available for these designs.
** For a more detailed version of this graph and other technical details, view the white paper Stratix II vs. Virtex-4 Power Comparison With Power Estimation Accuracy (PDF)

Hardware Power Comparisons of Stratix II & Virtex-4 FPGAs

In Figure 2, we now compare dynamic power for the same set of designs from Figure 1, which were selected to provide coverage of many FPGA functions. Stratix II FPGAs exhibit a substantial dynamic power advantage on nearly all RAM configurations, and consume equivalent or better dynamic power in block-level logic and digital signal processing (DSP) designs. The results for the full HDL customer design, Beamforming, show that Stratix II FPGAs have a 47 percent advantage.

Figure 2. Stratix II Dynamic Power Relative to Virtex-4, Based on Hardware Measurements

Figure 2. Stratix II Dynamic Power Relative to Virtex-4, Based on Hardware Measurements

Note:
* For a more detailed version of this graph and other technical details, view the white paper Stratix II vs. Virtex-4 Power Comparison With Power Estimation Accuracy (PDF).

To compare total device power of each FPGA, power must be separated into its components. Static power varies significantly from device to device, which means worst-case specifications should be used to compare FPGAs (hardware measurements are meaningless). Unlike static power, dynamic power varies little from device to device, enabling meaningful hardware-based comparisons of competing products.

More power comparisons between Stratix II and Virtex-4 FPGAs (including worst-case static and I/O power) can obtained from the Stratix II vs. Virtex-4 Power Comparison page, or, alternatively, all comparisons (with technical background information) are available in the white paper Stratix II vs. Virtex-4 Power Comparison With Power Estimation Accuracy (PDF).

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