Stratix II Devices & the Nios II Processor
Unparalleled Processing Power
Based on the wildly successful first generation Nios processor, the Nios II ® family of embedded processor delivers three processor cores to address an even wider range of embedded processing applications. Designers can choose from a high-performance core (over 200 DMIPS), a low-cost core (as low as 35 cents in logic) and a performance-/cost-balanced standard core. The Nios II family of processors addresses tasks such as:
- Implementing complex state machines
- Off-loading existing processors
- Performing I/O and data-processing tasks
- Configuring FPGAs remotely
- Accelerating digital signal processing (DSP) algorithms
The advanced architectural features of Stratix™ II FPGAs, combined with the Nios II embedded processors, offer unparalleled processing power to meet the needs of high-bandwidth systems. With Nios II processor-based systems (including a processor core and peripherals) starting at around 2,000 equivalent logic elements (LEs) Stratix II devices can easily fit complete system functions into a single device, satisfying the needs of networking, telecommunications, digital signal processor, and mass storage applications.
Figure 1 shows an example of multiple Nios II processors within a single Stratix II FPGA in a packet-processing networking design.
Figure 1. Nios Processors in a Stratix II Device for I/O Processing
Notes to Figure 1:
- MAC = Media access control
- DMA = Direct memory access
FPGA Device Architecture
Based on the success of the high-performance Stratix device family, the Stratix II FPGA architecture provides further technology enhancements that benefit complex intellectual property (IP) blocks, such as the Nios II embedded processor, both in terms of higher fMAX and lower resource utilization.
The Stratix II FPGA logic structure has been enhanced to allow it to perform certain frequently used functions efficiently, such as implementing 2 x 4:1 multiplexers in the equivalent of two LEs, compared with four in previous architectures. This works well with system blocks such as the Avalon™ switch fabric. The Stratix II FPGA’s wide input function support means that as the system increases in complexity, the performance penalty will also be reduced.
The Nios II processor includes several CPU-optimization options, which allow it to benefit from the Stratix II device’s digital signal processing (DSP) blocks, which can implement a single cycle-multiply function in a single DSP block. This implementation can save 370 LEs and hundreds of clock cycles when compared to a soft implementation. In the same way, the Stratix II FPGA adaptive logic modules (ALMs) ternary adder support further reduces the size of the Nios CPU’s arithmetic logic unit (ALU).
The embedded DSP blocks in the Stratix II device architecture also provide the perfect complement to Nios II custom instructions and other hardware acceleration units. DSP designers can now create DSP algorithms and complex math routines in high-performance hardware DSP blocks and access them as regular software routines or implement them as custom instructions to the Nios CPU. For example, in a voice-over-IP (VOIP) application, an echo-cancellation algorithm can be implemented in hardware and directly executed in software using a custom instruction. This gives designers the flexibility and portability of high-level software design while maintaining the performance benefits of parallel hardware operations in FPGAs—without resorting to excessive clock speeds.
The Stratix II device's TriMatrix™ memory caters to all the memory needs of a typical system-on-a-programmable-chip (SOPC) system. Each M-RAM block offers a 64-Kbyte segment, which can easily be joined to others to provide large amounts of on-chip data and instruction storage. Using just the M-RAM blocks, the user can give the Nios processor up to 576 Kbytes of memory in the Stratix II EP2S180 FPGA.
The Nios II processors also features instruction and data cache. Users can add instruction or data caches sized from 512 bytes to 64 Kbytes. The abundant TriMatrix memory blocks can implement on-chip cache memory for accelerating off-chip memory access and significantly increasing overall software performance in embedded systems.
Stratix II FPGAs & Nios II Processors: A Complete SOPC Solution
The Stratix II architecture is ideal for the block-based design methodology that is required for designing large systems using pre-optimized IP modules or re-using existing design modules.
Altera's SOPC Builder automated system development tool provides designers with a powerful platform for composing bus-based systems out of common system components such as processors, peripherals, and memory interfaces. SOPC Builder-generated systems (such as the one shown in Figure 2) are pre-optimized IP blocks that benefit significantly from the Stratix II architecture.
Figure 2. Typical SOPC Builder-Generated System
Note to Figure 2:
- JTAG = Joint Test Action Group
The Nios II peripherals and interfaces library web page has more details on the peripherals available for the Nios II processors.
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