Signal integrity is crucial in digital design because system speeds and clock edge rates continue to increase. To improve signal integrity, both single-ended and differential signals should be properly terminated. Termination can be implemented with external termination resistors on a board, or with on-chip termination technology. Figure 1 compares the integrity of a signal without termination against one using Altera's Stratix® II device on-chip termination.
Figure 1. Stratix II Device On-Chip Termination Improves Signal Integrity
Stratix II devices support both on-chip termination and external termination schemes, as shown in Table 1.
| Table 1. Termination Solutions Support | ||
| Termination Type | On-Chip | External |
|---|---|---|
| Series | Yes | Yes |
| Parallel | Yes | Yes |
| Differential | Yes | Yes |
On-Chip and Off-Chip Termination Benefits
On-chip termination eliminates the need for external resistors and simplifies the design of a PCB; Stratix II device on-chip termination benefits are described in Table 2.
| Table 2. Benefits of Stratix II Device On-Chip Termination | |
| Benefit | Description |
|---|---|
| Improved Signal Integrity | On-chip termination eliminates stub effects and helps to prevent reflections on the transmission line. |
| Simpler Board Design | On-chip termination minimizes the need for external resistors, allowing you to use fewer resistors, fewer board traces, and less board space, resulting in a simpler board layout. |
| Lower Cost | With on-chip termination, fewer resistors, fewer traces, and less space are needed on the board, which means less time spent in layout. Reducing your layout time and the number of components on the board can result in lower overall system costs. |
| Increased System Reliability | System reliability increases because on-chip termination reduces the number of components from the PCB. |
Termination with external resistors, on the other hand, provides tighter tolerance and is recommended for designs with stringent impedance tolerance requirements. Altera provides an external termination design kit with recommendations for low-cost, small-form factor resistor packs, board schematics and layout examples, along with simulation and test results. Figure 2 shows how off-chip termination is implemented using resistor packs.
Figure 2. Off-Chip Termination Using Resistor Packs
Series Termination
Stratix II devices support on-chip series termination for LVTTL, LVCMOS, SSTL-18, and SSTL-2 single-ended I/O standards (shown in Table 3). The on-chip termination is provided at the output signal to match the impedance of the transmission line, typically 25 or 50Ω. You can use this termination in many general-purpose applications and to interface with DDR SDRAM memories.
| Table 3. Supported I/O Standards for Series Termination | |
| Standard | Resistance ( ) |
|---|---|
| 3.3-V, 2.5-V, 1.8-V, 1.5-V LVTTL | 25 or 50 |
| 3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS | 25 or 50 |
| SSTL-18, SSTL-2 (Class I) | 25 |
| SSTL-18, SSTL-2 (Class II) | 25 |
Parallel Termination
Stratix II devices support on-chip parallel termination for SSTL and HSTL single-ended I/O standards (refer to Table 4). The on-chip parallel termination can be set to 50Ω. You can use this termination when implementing interfaces with external memories such as the DDR SDRAM and QDRII SRAM memories.
|
Table 4. Supported I/O Standards for Parallel Termination |
|
|
Standard |
Resistance ( |
|
SSTL-18, SSTL-2 (Class I) |
50 |
|
SSTL-18, SSTL-2 (Class II) |
50 |
|
1.8-V HSTL, 1.5-V HSTL (Class I) |
50 |
|
1.8-V HSTL, 1.5-V HSTL (Class II) |
50 |
|
1.2-V HSTL |
50 |
Stratix II devices support parallel termination through external resistors. Altera provides an external termination design kit with recommendations for low-cost, small-form factor resistor packs, board schematics and layout examples, along with simulation and test results.
Differential Termination
You use differential termination in system applications that require support for high-speed interface protocols, such as SPI-4.2, SFI-4, XSBI, RapidIO™, HyperTransport™, NPSI, and UTOPIA IV standards.
Stratix II devices support LVDS and HyperTransport input on-chip differential termination. The value of the on-chip termination resistor, RD, shown in Figure 3 is 100Ω.
Figure 3. On-Chip Differential Termination
