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Performance Leadership | |
Power Optimized |
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Density Leadership | |
Rich Feature Set |
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Signal Integrity Leadership |
Implement your high-density logic design with Stratix® II FPGAs and get higher performance and better signal integrity in the smallest possible device. Whether your design is for a single device to prototype an ASIC, or is destined for volume production, you can benefit from using Stratix II FPGAs with the knowledge that you can migrate to HardCopy® II ASICs should business conditions require it.
Key Stratix II FPGA features include:
- A new and innovative logic structure
- A rich feature set including high-performance DSP blocks and on-chip memories
- High-speed I/O pins and external memory interfaces
- A design security feature to protect your intellectual property
- A path to low-cost, high-density logic with HardCopy II ASICs
Stratix II FPGAs are manufactured on TSMC's 90-nm, low-k dielectric process technology with up to 180K equivalent logic elements (LEs) and 9 Mbits of embedded memory. While achieving high performance and density, Stratix II devices are also optimized for total device power. Altera's unique and patented redundancy technology dramatically increases yields and lowers device costs, so Altera can deliver Stratix II FPGAs in high volume today.
Reach the Highest Performance and Productivity Levels
With the highly efficient 8-input fracturable look-up table (LUT) logic structure, embedded adders, an abundance of registers in the adaptive logic module (ALM), DSP blocks, high-speed I/O pins, and Quartus® II design software support, Stratix II FPGAs deliver tomorrow's performance today with extra system-level margins.
Quartus II software provides a comprehensive all-in-one suite of synthesis, optimization, and verification tools that utilize extremely powerful algorithms. This tool suite dramatically improves your productivity (compared to traditional high-density FPGA design flows) by providing faster timing closure.
Low Risk and Low-Cost ASIC Migration Path
With support for migration to HardCopy II ASICs, Stratix II FPGAs offer the industry’s only seamless development path from FPGA prototyping to high-volume, low-cost ASIC production. HardCopy II devices further increase performance and reduce power consumption over the FPGA implementation and offer significantly lower unit costs.
Stratix II GX FPGAs—Transceivers with Integrity
The Stratix II GX family is Altera's third generation of FPGAs with embedded transceivers. Built using the Stratix II FPGA fabric, the Stratix II GX family integrates up to 20 serializer/deserializer (SERDES)-based transceivers on a single device. Through careful selection of data-rates and a new clocking structure, Stratix II GX devices support a broad spectrum of protocols while dissipating significantly less power than competing solutions.
Best-in-Class Features
Stratix II devices improve on the features that set new standards in FPGAs (shown in Figure 1). New device capabilities—such as the new logic structure and design security technology—round out the industry’s most advanced FPGA feature set.
Figure 1. Stratix II Device Floorplan
Enhance Your Stratix II Design Skills—Register Today
Altera® Technical Training courses ensure that designers' programmable logic skills are up-to-date with the latest tools and technology. Designers can take advantage of the newest features in Altera’s Stratix II devices and get design tips for the Quartus II software and related EDA tools to achieve the highest performance and smallest footprint designs. This results in cost savings and faster time to market.
The Altera Technical Training course catalog includes the following Stratix II FPGA-specific courses:
- Statix II Device Family Literature
- Fundamental Design Techniques for Stratix & Stratix II Devices
- Advanced Design Techniques for Stratix & Stratix II Devices
