Stratix II Device Family Questions & Answers
Following are the most frequently asked questions about Altera® Stratix® II devices.
General
Performance
Memory
Digital Signal Processing Blocks
Design Security
System Clock Management
Source-Synchronous Signaling & High-Speed Interfaces
On-Chip Termination
Software & Intellectual Property
Device Configuration
Nios Embedded Processor
HardCopy Devices
General
What is the Stratix II device family?
Altera's Stratix II device family is the newest high-density FPGA family from Altera. Stratix II devices feature a brand new, unique architecture comprised of an innovative logic structure, allowing designers to pack more functionality into less space, thereby reducing developments costs. Combined with the 90-nm process technology, the Stratix II family delivers on average 50 percent faster logic performance, more than twice the logic capacity, and is typically 40 percent lower cost than first generation Stratix devices allowing designers to leverage the advantages of programmable technology in a much wider set of applications.
What is the key technology in this innovative new architecture?
The adaptive logic module (ALM) is the fundamental innovation in the Stratix II architecture. An ALM is the basic building block of logic in the Stratix II architecture. It provides advanced features with efficient logic utilization and fast performance. Each ALM contains two adaptive look-up tables (ALUTs). With up to eight inputs to the combinational logic block, one ALM can implement up to two independent functions each of varying widths. One ALM can also implement any function of up to six inputs and certain seven-input functions. In addition to the two ALUTs, each ALM contains two programmable registers, two dedicated full adders, a carry chain, an adder tree chain, and a register chain that make more efficient use of device logic capacity. Stratix II devices have more than twice the logic of Stratix FPGAs with close to 180,000 equivalent logic elements (LEs).
What are the benefits of the ALM?
The Stratix II family's innovative ALM-based logic structure delivers more logic capacity and faster performance in a smaller physical area. By enabling adjacent look-up tables to share logic and inputs, ALMs reduce the logic resources required for any given function and the number of logic levels needed in a given critical path. In addition, two independent functions can be packed into a single ALM, further reducing logic resource requirements. Composed of combinational, arithmetic, and register logic, an ALM is 2.5 times more powerful and efficient than logic structures used in previous FPGA architectures.
Are Stratix II ALMs backward-compatible with Stratix LEs?
Yes, while Stratix II ALMs are much more powerful and efficient as compared to Stratix LEs, the ALM features a backward-compatibility mode. This mode allows customers to easily migrate their designs from Stratix devices and other FPGA architectures to Stratix II devices. Altera's Quartus II design software will automatically take advantage of the new ALM to improve a design's performance and logic efficiency.
What new key features are offered in Stratix II devices?
Altera's Stratix II FPGAs introduce a suite of new features that expand the capabilities of FPGAs in high-performance applications.
- Design Security—Each Stratix II device can be securely programmed using a 128-bit key based on the advanced encryption standard (AES). The key deciphers an encrypted configuration file generated by the Quartus® II software and is stored in an external configuration device.
- 1.040-Gbps Differential Source-Synchronous Signaling—Stratix II devices offer up to 152 receiver and 156 transmitter source-synchronous channels that support data transfer rates up to 1.040 Gbps for differential I/O standards such as LVDS and the HyperTransport™ standard.
- Dynamic Phase Alignment (DPA)—The embedded dynamic phase alignment circuitry in Stratix II devices simplifies printed circuit board (PCB) layout. DPA eliminates the signal alignment issues caused by source-synchronous signaling techniques' skew-inducing effects.
How do Stratix II devices compare to Stratix devices?
Stratix II devices offer a new and innovative logic structure and are built using 90-nm process technology. Stratix II devices deliver on average 50 percent faster logic performance, more than twice the logic capacity, and are typically 40 percent lower cost than first generation Stratix devices. To provide system designers with even more flexibility and functionality, Stratix II devices are outfitted with an enhanced set of the same system-level features first introduced in Stratix devices, such as TriMatrix™ memory, digital signal processing (DSP) blocks, and external memory interfaces. The table below provides a detailed comparison of the two device families.
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Table 1. Stratix II & Stratix Technology Feature Comparison
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|
Technology & Features
|
Stratix II
|
Stratix
|
|
Process Technology
|
90nm
|
0.13µm
|
|
Logic Structure
|
Adaptive Logic Module
(Enhanced LUT-based structure with support for functions up to 7 inputs)
|
Logic Element
(Standard 4-input LUT-based structure)
|
|
Logic Density
|
Up to 179,400 equivalent logic elements
|
Up to 79,040 logic elements
|
|
TriMatrix Memory
|
Up to 9 Mbits of embedded memory
|
Up to 7 Mbits of embedded memory
|
|
External Memory Interface Support
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DDR2, RLDRAM II, QDRII, DDR, SDR SDRAM
|
RLDRAM II, QDRII, QDR, ZBT, DDR, SDR SDRAM
|
|
DSP Blocks
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Up to 384 18x18 Multipliers
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Up to 88 18x18 Multipliers
|
|
Enhanced & Fast Phase-Locked Loops (PLLs)
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Up to 4 enhanced and 8 fast PLLs
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Up to 4 enhanced and 8 fast PLLs
|
|
Global Clock Networks
|
Up to 16 global clock networks
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Up to 16 global clock networks
|
|
Source-Synchronous Signaling
|
Up to 1.040-Gbps data rates for LVDS and HyperTransport standards
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Up to 840-Mbps data rates for LVDS, LVPECL, 3.3-V PCML, and HyperTransport standards
|
|
Source-Synchronous Protocol Support
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SPI-4.2, SFI-4, XSBI, HyperTransport, RapidIO,
NPSI, UTOPIA IV
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SPI-4.2, SFI-4, XSBI, HyperTransport, RapidIO, NPSI, UTOPIA IV
|
|
Dynamic Phase Alignment
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Yes
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No
|
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Single-Ended I/O Support
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SSTL-2 (I & II), SSTL-18 (I & II), 1.8-V HSTL (I & II), 1.5-V HSTL (I & II), 3.3-V PCI, 3.3-V PCI-X 1.0, 3.3-V/2.5-V/1.8-V LVTTL, 3.3-V/2.5-V/1.8-V/1.5-V LVCMOS
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SSTL-3 (I & II), SSTL-2 (I & II), SSTL-18 (I & II), 1.8-V HSTL (I & II), 1.5-V HSTL (I & II), 3.3-V PCI, 3.3-V PCI-X 1.0, GTL, GTL+, 3.3-V AGP (1x and 2x), CTT, 3.3-V/2.5-V/1.8-V LVTTL, 3.3-V/2.5-V/1.8-V/1.5-V LVCMOS
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|
Design Security
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Advanced Encryption Standard (AES) algorithm with
128-bit key
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No
|
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On-Chip Termination
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Series & Differential
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Series & Differential
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Nios® Processor Support
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Yes
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Yes
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HardCopy Support
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Mid-2005
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Now
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How many members are there in the Stratix II device family, and in what packages will they be available?
The Stratix II device family includes six members ranging in logic density from 15,600 to 179,400 equivalent LEs with up to 9 Mbits of embedded RAM, up to 384 18x18 multipliers, and up to 12 PLLs. Stratix II devices are available in six high-performance flip-chip FineLine BGA® packages (484 to 1,508 pins) with vertical migration support.
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Table 2. Stratix II Device Family Overview
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|
Device
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ALMs
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Equivalent LEs
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M512 Blocks
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M4K Blocks
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M-RAM Blocks
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Total Memory Bits
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DSP Blocks
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18x18 Multipliers
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PLLs
|
|
EP2S15
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6,240
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15,600
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104
|
78
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0
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419,328
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12
|
48
|
6
|
|
EP2S30
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13,552
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33,880
|
202
|
144
|
1
|
1,369,728
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16
|
64
|
6
|
|
EP2S60
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24,176
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60,440
|
329
|
255
|
2
|
2,544,192
|
36
|
144
|
12
|
|
EP2S90
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36,384
|
90,960
|
488
|
408
|
4
|
4,520,448
|
48
|
192
|
12
|
|
EP2S130
|
53,016
|
132,540
|
699
|
609
|
6
|
6,747,840
|
63
|
252
|
12
|
|
EP2S180
|
71,760
|
179,400
|
930
|
768
|
9
|
9,383,040
|
96
|
384
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12
|
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Table 3. Stratix II Package Offerings & User I/O Counts
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|
Device
|
484-Pin FBGA (1)
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484-Pin Hybrid FBGA
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672-Pin FBGA
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780-Pin FBGA
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1,020-Pin FBGA
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1,508-Pin FBGA
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|
EP2S15
|
342
|
-
|
366
|
-
|
-
|
-
|
|
EP2S30
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342
|
-
|
500
|
-
|
-
|
-
|
|
EP2S60
|
334
|
-
|
492
|
-
|
718
|
-
|
|
EP2S90
|
-
|
308 (2)
|
-
|
534 (2)
|
758
|
902
|
|
EP2S130
|
-
|
-
|
-
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534 (2)
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742
|
1,126
|
|
EP2S180
|
-
|
-
|
-
|
-
|
742
|
1,170
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Notes to Table 3:
1. FBGA = FineLine BGA package.
2. User I/O counts are preliminary and subject to change.
When will Stratix II devices be available?
Engineering samples of the first member of the Stratix II device family, the EP2S60 device, will be available in Q2 2004, with the remaining family members rolling out in the next 6 months. Production devices will be available in the first half of 2005.
What is the pricing for the Stratix II device family?
Pricing for Stratix II devices is dependent on the density, package, performance, and volume quantities of the devices ordered. Typically, Stratix II pricing is 40 percent lower than Stratix pricing. Please contact Altera's sales representatives and distributors for more specific pricing information.
What speed grades will be available?
Stratix II devices are offered in three speed grades: -3, -4, and -5, with -3 being the fastest and -5 the slowest.
What process technology is used to produce Stratix II devices?
Stratix II devices are based on a 1.2-V, 90-nm, 9-layer-metal, all-layer-copper process technology from TSMC, extending the process-leadership advantages Altera gained at the 0.13-µm node with the first-generation Stratix family. Stratix II devices will use a low-K dielectric and will be manufactured on 300-mm wafers.
Are Stratix II devices pin-compatible with Stratix devices?
No, they are not since Stratix II devices are based on a completely new logic structure and process technology. Customers can, however, easily re-target their designs for Stratix II devices using third-party EDA development tools and Altera's Quartus® II design software.
How do Stratix II device ordering codes relate to their respective densities?
Stratix II device ordering codes represent the capacity of the device and are based on the number of equivalent LEs in the device. All Stratix II device ordering codes begin with "EP2S". The digits that follow indicate the number of equivalent LEs divided by a factor of 1,000. The smallest Stratix II device, for example, is the EP2S15 device, which has 15,600 equivalent LEs.
Performance
What is the overall push-button performance improvement achievable in Stratix II devices over Stratix devices?
The industry's fastest FPGAs, Stratix II devices offer on average 50 percent faster push-button performance compared to Stratix FPGAs. This performance improvement results from combining 90-nm production and the ALM-based logic structure with the powerful features of the Quartus II version 4.0 design software. (Push-button performance refers to the maximum system frequency achieved with an existing design, using the default design flow available in the Quartus II software.)
How does the performance for the enhanced features in Stratix II devices compare to Stratix devices?
The 90-nm process technology and the ALM-based architecture allow Stratix II devices to offer performance levels unmatched by any previous FPGA family. The table below provides a Stratix to Stratix II performance comparison.
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Table 4. Stratix II & Stratix Performance Comparison
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Feature
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Stratix II
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Stratix
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M512 RAM Blocks
|
380 MHz
|
319 MHz
|
|
M4K RAM Blocks
|
400 MHz
|
290 MHz
|
|
M-RAM Blocks
|
400 MHz
|
287 MHz
|
|
DSP Blocks
|
420 MHz
|
335 MHz
|
|
Source-Synchronous Signaling
|
1.040 Gbps (1,040 Mbps)
|
840 Mbps
|
|
External Memory Interfaces
|
300 MHz
|
200 MHz
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Memory
What is TriMatrix memory, and what features does it support?
First introduced in Stratix devices, TriMatrix memory is a highly efficient high-density memory structure made up of three sizes of memory blocks, each optimized to target a different class of applications. The Stratix II TriMatrix memory structure offers up to 9 Mbits of storage capacity and new features such as "pack mode" and "address enable". It integrates 512-Kbit M-RAM blocks with several smaller 512-bit M512 and 4-Kbit M4K blocks to provide a unique solution to applications requiring either large amounts of memory bits or high memory bandwidth. For example, M512 blocks can be used for first-in first-out (FIFO) functions and clock domain buffering functions requiring only limited memory, M4K blocks can be used for medium-sized memory applications such as asynchronous transfer mode (ATM) cell processing, and 512-Kbit M-RAM blocks can be used to store Nios microprocessor code or for other storage-intensive applications such as IP packet buffering. All memory blocks include extra parity bits for error control, mixed-width mode, and mixed-clock mode support. In addition, the M4K and M-RAM blocks support true dual-port mode and byte masking for advanced write operations.
Digital Signal Processing Blocks
What are DSP blocks and what are their capabilities?
Stratix II DSP blocks are high-performance embedded processing units that combine with device TriMatrix memory and logic elements to allow designers to efficiently implement DSP algorithms, including: filtering, compression, chip-rate processing, equalization, digital intermediate frequency, transforms, and modulation. The blocks are designed to eliminate performance bottlenecks in DSP applications, while providing predictable and reliable performance and saving resources. Input, output, and optional intermediate pipelining registers are included in each block to deliver performance levels of over 420 MHz and bandwidth capabilities up to 3-GMAC operations per second. Each DSP block offers multipliers, adders, subtractors, accumulators, and summation units frequently required in typical DSP algorithms. Using these DSP blocks, Stratix II devices can easily meet the DSP throughput requirements of emerging standards and protocols such as JPEG2000, MPEG-4, 802.11x, CDMA2000, 1x EV DV, HSDPA, and W-CDMA.
What benefits are associated with this type of DSP block architecture?
Similar to the DSP block in Stratix devices, the first FPGAs with complete DSP functionality, the DSP block in Stratix II devices is composed of multipliers, adders, subtractors, accumulators, a summation unit, and pipeline registers. In addition, the DSP block in Stratix II devices supports rounding and saturation of numbers in the Q1.15 number format. The rounding and saturation block simplifies the porting of digital signal processor-based software functions to a hardware implementation in FPGAs. The Stratix II DSP blocks improve device performance and maximize resources. Both the multiplication and subsequent accumulation/addition/subtraction stages are completely isolated within the DSP block, so that DSP performance is not impacted by other functions the device is performing. This is a critical design feature, because the processing capabilities of FPGAs outperform industry-standard digital signal processors in computation-intensive applications that require parallel operations or time-domain multiplexing (TDM).
What is the benefit of increasing the number of DSP blocks in Stratix II devices?
At the same density range, Stratix II devices offer two times more DSP blocks than Stratix devices. When comparing the largest member of both families, Stratix II devices offer four times more DSP blocks than Stratix devices. Quadrupling the number of DSP blocks available in Stratix II devices, as compared to first-generation Stratix devices, extends Stratix II device DSP algorithm implementation capabilities. Stratix II devices offer up to 96 DSP blocks capable of performing up to 384 parallel multiplications and providing a combined data throughput of up to 288 GMACS. That is 48 times more parallel multiplications and over 30 times greater throughput than that offered by a discrete digital signal processor.
Design Security
What is the difference between design security features offered in Stratix II devices and other FPGAs?
Stratix II devices use the advanced encryption standard (AES) algorithm with 128-bit key to encrypt the configuration bitstream. Selected by the National Institute of Standards and Technology (NIST) and adopted by the United States government to protect sensitive information, AES is the most advanced encryption algorithm available today. The Stratix II devices are the industry's first FPGAs to support configuration bitstream encryption using AES and a 128-bit non-volatile key. Other FPGA vendors support Triple DES bitstream encryption using a battery to power up or back up the volatile key. Such approaches are very difficult to implement, increasing board-level concerns regarding possible system malfunctions and the need for redundancy. When the battery fails in the field, for example, the FPGA will not power on, causing the board to malfunction. Stratix II devices simplify system design by eliminating the need for a constant power source. Stratix II devices support the best configuration bit stream encryption available in the FPGA market.
What markets benefit from the Stratix II design security feature?
In today's government agencies, military, and highly competitive commercial environments, design security is an important consideration for digital designers who want a very high level of protection for their designs. The Stratix II design security feature addresses new applications where both the flexibility of programmable logic and design protection are required.
How can designers implement the design security feature in Stratix II devices?
Stratix II devices offer a secure configuration flow, which can be implemented in three steps:
- The 128-bit AES key is programmed into non-volatile storage in the Stratix II device.
- The Quartus II design software uses the same AES key to generate an encrypted configuration file, which is then stored in flash memory or a configuration device(s).
- At power-up, the flash memory or configuration device(s) sends the encrypted configuration file to the Stratix II device, which then uses the stored AES key to decrypt the file and configure itself.
System Clock Management
How many PLLs are embedded in Stratix II devices?
Up to 12 on-chip PLLs—capable of precise frequency synthesis and timing management—are available on the largest Stratix II devices.
What types of PLLs are available in Stratix II devices?
Stratix II devices support two types of PLLs: enhanced PLLs and fast PLLs. Both provide advanced frequency synthesis capabilities.
What is the difference between enhanced and fast PLLs?
Feature-rich enhanced PLLs are used for general-purpose applications that support advanced capabilities such as external feedback, clock switchover, phase and delay control, PLL reconfiguration, spread-spectrum clocking, and programmable bandwidth. Fast PLLs deliver the high-speed outputs needed to manage high-speed differential I/O interfaces, as well as other general-purpose clocking management capabilities, such as clock multiplication and phase shifting.
What are the benefits of Stratix II PLLs?
Stratix II PLLs integrate capabilities that were previously only available in high-end, discrete PLL devices. As a result, Stratix II devices can manage board-level clock systems, effectively reducing design complexity and overall cost. Each PLL has multiple outputs that can drive any of the 48 system clocks available in Stratix II devices, giving designers complete control over their clocking requirements. Each also provides full frequency synthesis capabilities (the ability to multiply up or divide down the clock frequency) and phase shifting to optimize I/O timing.
Source-Synchronous Signaling & High-Speed Interfaces
What is dynamic phase alignment?
Stratix II device dynamic phase alignment, which is essential to support many emerging high-speed interface protocols, continuously compares incoming data on a channel-by-channel basis with an incoming system clock. It removes channel-to-channel and clock-to-channel timing variations introduced by unmatched board trace lengths, jitter, and other skew-inducing effects.
Why is DPA important?
The Stratix II family's embedded DPA function dramatically simplifies printed circuit board design, helping to minimize the challenges involved in implementing high-speed, source-synchronous data transfer applications, eliminates signal issues introduced by skew-inducing effects and enables Stratix II source-synchronous signals with 1.040-Gbps data rates. In addition, emerging bus transfer protocols such as SPI-4.2 require DPA.
What are the benefits of hard DPA as compared to soft DPA?
The hard DPA used in Stratix II devices incorporates the DPA feature directly into embedded silicon on the source-synchronous channels, providing verifiable, reliable skew reduction and higher speed transmission. Soft DPA is implemented using programmable logic and clock resources. It occupies valuable logic resources, can rapidly consume device global clocks and PLLs, and can be susceptible to errors caused by temperature and voltage changes. The Stratix II hard DPA implementation avoids these issues and ensures errorless data transmission. Additionally, since the hard DPA is embedded in the FPGA, designers do not need to spend extra time characterizing it. Altera automatically characterizes the hard DPA over temperature. A soft DPA implementation requires the designer to do the characterization.
What high-speed differential I/O electrical standards do Stratix II devices support?
Altera has proven expertise in high-speed differential I/O design and continues to support LVDS and HyperTransport in Stratix II devices. The Altera differential I/O solution, unlike others in the programmable logic industry, uses dedicated, high-speed circuitry to maximize device throughput. This circuitry includes optimized transmitter and receiver I/O buffers, serialization/deserialization circuitry, high-performance fast PLLs, and enhanced byte alignment capabilities. Stratix II devices also offer up to 152 receiver and 156 transmitter channels, supporting source synchronous signaling for data transfer rates as high as 1.040 Gbps.
What high-speed I/O interface protocols are supported in Stratix II devices?
Stratix II devices support many of the latest high-bandwidth bus protocols, including the SPI-4.2, SFI-4, XSBI, HyperTransport™, RapidIO™, NPSI, and UTOPIA IV protocols for applications such as interface bridging, backplanes, and chip-to-chip communications.
Which external memory interfaces do Stratix II devices support?
The Stratix II device family meets the performance requirements of the latest SRAM and DRAM devices, as shown in Table 5. External memory devices can be easily connected to Stratix II devices to provide additional storage capacity outside of the abundant on-chip TriMatrix memory resources without causing performance bottlenecks. Designers can purchase Altera- or third-party-developed IP memory controller cores, download royalty-free reference designs from the Altera web site, or develop their own customized cores for their specific applications.
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Table 5. High-Performance External Memory Interface Support in Stratix II Devices
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|
Memory Technology
|
I/O Standard
|
Bus Width
|
Maximum Clock Speed
|
|
SDR SDRAM
|
LVTTL
|
72 bits
|
200 MHz
|
|
DDR SDRAM
|
SSTL-2 Class I, II
|
72 bits
|
200 MHz
|
|
DDR2 SDRAM
|
SSTL-1.8 Class I, II
|
72 bits
|
267 MHz
|
|
RLDRAM II
|
SSTL-2 Class I, II
|
36 bits
|
300 MHz
|
|
QDR SRAM
|
HSTL-1.8 Class I, II
|
36 bits
|
167 MHz
|
|
QDRII SRAM
|
HSTL-1.8 Class I, II
|
36 bits
|
250 MHz
|
On-Chip Termination
Why type of termination does Stratix II devices support?
Signal integrity has become crucial in digital design because system speeds and clock edge rates continue to increase. To improve signal integrity, both single-ended and differential signals should be properly terminated. Termination can be implemented with external termination resistors on a board or with on-chip termination technology. Stratix II devices provide on-chip termination that supports series and differential terminations.
Software & Intellectual Property
What version of the Quartus II design software will support Stratix II devices?
Stratix II devices are supported by Quartus® II software version 4.0, the industry's most advanced software available for high-density FPGA designs. Developed with many new ASIC-like design capabilities, the Quartus II design software gives customers feature-rich synthesis and simulation tools, as well as an easy-to-use interface, to take full advantage of Stratix II FPGA performance and design benefits. The Quartus II software also integrates seamlessly with all of the leading third-party synthesis and simulation tools. The free version of the software, Quartus II web edition software version 4.0, will support the Stratix II EP2S15 devices and will be available for download from the Altera web site at www.altera.com. Designers can leverage this new version of the Quartus II software to deliver Stratix II device-based designs that outperform existing Stratix designs by up to 50 percent.
Which third-party tools will support Stratix II devices?
In addition to the Quartus II integrated synthesis tool, synthesis and simulation tools from leading EDA vendors Mentor Graphics, Synplicity, Cadence, and Synopsys all support the Stratix II device family, ensuring the highest quality of results in Altera devices.
Which third-party synthesis vendors support the new ALM?
Mentor Graphics Precision 2003c and Synplicity Synplify 7.3.5 software synthesis tools fully support the Stratix II ALM.
What IP cores will be available for Stratix II devices?
Altera offers off-the-shelf IP cores optimized for Stratix II devices, along with an extensive library of standard IP cores. Each core has been optimized to specifically take advantage of the architectural features of the Stratix II family, including the new logic structure and advanced I/O capabilities. More information is available at the Altera IP MegaStore ™ web site.
Device Configuration
What configuration devices will be available to support the Stratix II devices?
Altera's low-cost serial configuration devices and enhanced configuration devices will support Stratix II devices.
What is the remote system upgrade feature?
The remote system upgrade feature allows designers to reconfigure Stratix II devices from a remote source, extending the product's lifespan while also saving time and costs. New configuration data can be sent to a system from a remote source, saved to an external memory device such as an advanced configuration device, and subsequently used to reconfigure the Stratix II device. The Stratix II device includes dedicated circuitry that ensures a successful re-configuration using the new application data. If an error occurs during this process, the Stratix II device automatically initiates re-configuration from the external memory device using safe, default factory-configured settings. With Stratix II devices, designers can now safely deploy system upgrades or bug fixes without the time-consuming process of visiting all locations to perform a manual re-configuration.
Nios Embedded Processor
Is the Nios embedded processor supported in Stratix II devices?
Yes, the 32-bit RISC Nios embedded processor offers a 30 percent performance improvement on Stratix II devices over Nios implementations on previous Altera architectures. Stratix II devices also feature continued support for Nios features such as the simultaneous multi-master Avalon™ switch fabric, custom instructions, and advanced debugging.
HardCopy Devices
Will Altera support Stratix II migration to HardCopy™ devices?
Yes, Altera will support a migration path from Stratix II FPGAs to HardCopy devices, giving customers the only prototype-to-production solution offered in the industry. HardCopy devices for Stratix II FPGAs deliver an additional increase in performance and lower power for volume applications, while significantly reducing risk and providing cost savings. At the same time, HardCopy devices provide identical functionality, supporting Stratix II device features such as TriMatrix memory, DSP blocks, high-speed interfaces, and PLLs. In addition, Quartus II design software provides a unified design flow facilitating the migration from Stratix II FPGAs to HardCopy devices. HardCopy devices for Stratix II FPGAs will be available in mid-2005.
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