Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature

High-End FPGAs       About Stratix Series    Stratix IV (E and GX)    Stratix III (L and E)    Stratix II (and GX)        Stratix II                Overview                Design Utilities                Features                Literature        Stratix II GX    Stratix (and GX)     Midrange FPGAs    Arria (GX)     Low-Cost FPGAs    Cyclone III    Cyclone II    Cyclone     CPLDs    MAX II (and G, Z)    MAX 3000A     ASICs       About HardCopy Series    HardCopy IV (E and GX)    HardCopy III    HardCopy II    HardCopy Stratix     Device-Specific Offerings    RoHS Compliant       Extended Temperature       Industrial Temperature       Military Temperature       Automotive Temperature     Configuration Devices    Enhanced Configuration    Serial Configuration     Mature Products       Product Listing

Home > Products > Devices > Stratix II (and GX) > Stratix II > Design Utilities > Designing with Stratix II FPGAs and Quartus II Software Print This Page Subscribe to Email Designing with Stratix II FPGAs and Quartus II Software The Quartus® II software enables you to create and deliver Stratix® II designs with unmatched levels of performance and faster time-to-market. Along with a broad portfolio of design-ready intellectual property (IP) cores, Quartus II software and Stratix II FPGAs deliver the most comprehensive programmable logic solution in the industry. The Leader in Productivity for High-Density FPGA Designs Quartus II software enables the highest levels of productivity and the fastest path to design completion for high-density Stratix II FPGA designs. You can dramatically improve your productivity compared to traditional high-density FPGA design flows by using the following productivity-enhancing features: Incremental compilation, an industry first, supports top-down and bottom-up, team-based design which delivers faster compilation times for design iterations while preserving performance. PowerPlay power analysis and optimization technology provides automated power optimization capabilities and helps you effectively manage power from design concept through implementation. SOPC Builder is a system-level tool that eliminates mundane and error-prone system integration tasks and allows you to build systems in minutes. Push-button physical synthesis technology and the automated Design Space Explorer simplifies design optimization. Extensive cross-probing support between tools helps identify and correct design issues. The pin planner feature (PDF) enables easy I/O pin planning, assignment, and validation. Complete command-line and tool command language (Tcl) scripting interfaces give you advanced scripting capabilities. Verification solutions include the following features: TimeQuest Timing Analyzer with native Synopsys Design Constraint (SDC) support Capability to update memory and constants in-system without reconfiguring the device Chip editor shows hierarchical views of a design implemented in an Altera® device SignalTap® II embedded logic analyzer and support for integration with external logic analyzers Integration with all leading third-party EDA verification tools and methodologies The Leader in Performance for High-Density FPGA Designs Quartus II software enables the highest levels of performance and the fastest path to design completion for high-density Stratix II FPGA designs. Quartus II software and Stratix II FPGAs offer a significant performance advantage compared to other high-density FPGA and software solutions: Performance Benchmarks—Stratix II FPGAs and Quartus II software offer the highest performance in the industry. Advanced Place-and-Route Algorithms—Offers the fastest push-button results in the industry. Design Space Explorer (PDF)—Quartus II software's design space explorer script increases average design performance by 20 percent, automatically applying combinations of netlist optimizations and advanced Quartus II software compiler settings. Physical Synthesis—Quartus II software's physical synthesis can re-wire logic connections, duplicate registers, and move registers to significantly improve overall circuit performance. Nios® II Processor—Optimized to operate at over 200 MHz, the Nios II/f fast core processor is designed for maximum performance. Only Parallel Development for FPGAs and ASICs Only Quartus II software provides seamless migration between Stratix II FPGA designs and Hardcopy® II ASIC design. By enabling compilation for the HardCopy series ASICs, Quartus II software provides the only risk-free path to higher performance and lower device costs. Related Links See What Customers Are Saying Quartus II Questions and Answers Introduction to Quartus II Manual (PDF)  Quartus II Development Software Handbook Rate This Page

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Devices | Design Software | Intellectual Property | Design Services | Dev. Kits/Cables | Literature  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation